74LV259 查看數據表（PDF） - NXP Semiconductors.

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74LV259

8-bit addressable latch

NXP Semiconductors. 

NXP Semiconductors

74LV259

8-bit addressable latch

1 A0

1 OF 8

2 A1 DECODER

3 A2

14 LE

15 MR

13 D

Fig 3. Functional diagram

5. Pinning information

Q0 4

Q1 5

Q2 6

Q3 7

8 LATCHES Q4 9

Q5 10

Q6 11

Q7 12

001aah120

5.1 Pinning

A0 1

A1 2

A2 3

Q0 4

Q1 5

Q2 6

Q3 7

GND 8

74LV259

16 VCC

15 MR

14 LE

13 D

12 Q7

11 Q6

10 Q5

9 Q4

001aah127

Fig 4. Pin configuration DIP16, SO16 and (T)SSOP16

terminal 1

index area

74LV259

A1 2

A2 3

Q0 4

Q1 5

Q2 6

Q3 7

VCC(1)

15 MR

14 LE

13 D

12 Q7

11 Q6

10 Q5

001aah117

Transparent top view

(1) The die substrate is attached to this pad using

conductive die attach material. It can not be used as

a supply pin or input.

Fig 5. Pin configuration DHVQFN16

5.2 Pin description

Table 2.

Symbol

A0

A1

A2

GND

Q[0:7]

Pin description

Pin

1

2

3

8

4, 5, 6, 7, 9, 10, 11, 12

Description

address input

address input

address input

ground (0 V)

latch output

74LV259_3

Product data sheet

Rev. 03 — 2 January 2008

© NXP B.V. 2008. All rights reserved.

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