7812 查看數據表（PDF） - Analog Devices
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7812 Datasheet PDF : 20 Pages
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PIN CONFIGURATIONS
DIP/SOIC/TSSOP
AD7811/AD7812
VREF 1
16 VDD
CREF 2
15 CONVST
VIN1
AGND
VIN2
VIN3
3
14 SCLK
4 AD7811 13 DIN
5
TOP VIEW
(Not to Scale) 12
DOUT
6
11 RFS
VIN4 7
10 TFS
A0 8
9 DGND
VREF 1
20 VDD
CREF 2
19 CONVST
VIN1 3
18 SCLK
AGND 4
17 DIN
VIN2 5 AD7812 16 DOUT
VIN3
6
TOP VIEW
(Not to Scale)
15
RFS
VIN4 7
14 TFS
VIN5 8
13 DGND
VIN6 9
12 A0
VIN7 10
11 VIN8
Pin(s)
AD7811
1
Pin(s)
AD7812
1
Name
VREF
2
3, 5–7
4
8
2
3, 5–11
4
12
CREF
VIN1–VIN4(8)
AGND
A0
9
13
10
14
11
15
DGND
TFS
RFS
12
16
13
17
14
18
15
19
16
20
REV. A
DOUT
DIN
SCLK
CONVST
VDD
PIN FUNCTION DESCRIPTIONS
Description
An external reference input can be applied here. When using an external precision
reference or VDD the EXTREF bit in the control register must be set to logic one. The
external reference input range is 1.2 V to VDD.
Reference Capacitor. A capacitor (10 nF) is connected here to improve the noise
performance of the on-chip reference.
Analog Inputs. The analog input range is 0 V to VREF.
Analog Ground. Ground reference for track/hold, comparator, on-chip reference and
DAC.
Package Address Pin. This Logic Input can be hardwired high or low. When used in
conjunction with the package address bit in the control register this input allows two
devices to share the same serial bus. For example a twelve channel solution can be
achieved by using the AD7811 and the AD7812 on the same serial bus.
Digital Ground. Ground reference for digital circuitry.
Transmit Frame Sync. The falling edge of this Logic Input tells the part that a new
control byte should be shifted in on the next 10 falling edges of SCLK.
Receive Frame Sync. The rising edge of this Logic Input is used to enable a counter in
the serial interface. It is used to provide compatibility with DSPs which use a continuous
serial clock and framing signal. In multipackage applications the RFS Pin can also be
used as a serial bus select pin. The serial interface will ignore the SCLK until it receives a
rising edge on this input. The counter is reset at the end of a serial read operation.
Serial Data Output. Serial data is shifted out on this pin on the rising edge of the serial
clock. The output enters a High impedance condition on the rising edge of the 11th
SCLK pulse.
Serial Data Input. The control byte is read in at this input. In order to complete a
serial write operation 13 SCLK pulses need to be provided. Only the first 10 bits are
shifted in—see Serial Interface section.
Serial Clock Input. An external serial clock is applied to this input to obtain serial data
from the AD7811/AD7812 and also to latch data into the AD7811/AD7812. Data is
clocked out on the rising edge of SCLK and latched in on the falling edge of SCLK.
Convert Start. This is an edge triggered logic input. The Track/Hold goes into its Hold
Mode on the falling edge of this signal and a conversion is initiated. The state of this
pin at the end of conversion also determines whether the part is powered down or not.
See operating modes section of this data sheet.
Positive Supply Voltage +2.7 V to +5.5 V.
–5–
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