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A29002

256K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory

AMIC Technology 

A29002/A290021 Series

Preliminary

256K X 8 Bit CMOS 5.0 Volt-only,

Boot Sector Flash Memory

Features

n 5.0V ± 10% for read and write operations

n Access times:

- 55/70/90/120/150 (max.)

n Current:

- 20 mA typical active read current

- 30 mA typical program/erase current

- 1 µA typical CMOS standby

n Flexible sector architecture

- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX3 sectors

- Any combination of sectors can be erased

- Supports full chip erase

- Sector protection:

A hardware method of protecting sectors to prevent

any inadvertent program or erase operations within

that sector

n Top or bottom boot block configurations available

n Embedded Erase Algorithms

- Embedded Erase algorithm will automatically erase

the entire chip or any combination of designated

sectors and verify the erased sectors

- Embedded Program algorithm automatically writes

and verifies bytes at specified addresses

General Description

The A29002 is a 5.0 volt-only Flash memory organized as

262,144 bytes of 8 bits each. The A29002 offers the

RESET function, but it is not available on A290021. The

256 Kbytes of data are further divided into seven sectors for

flexible sector erase capability. The 8 bits of data appear on

I/O0 - I/O7 while the addresses are input on A0 to A17. The

A29002 is offered in 32-pin PLCC, TSOP, and PDIP

packages. This device is designed to be programmed in-

system with the standard system 5.0 volt VCC supply.

Additional 12.0 volt VPP is not required for in-system write

or erase operations. However, the A29002 can also be

programmed in standard EPROM programmers.

The A29002 has the first toggle bit, I/O6, which indicates

whether an Embedded Program or Erase is in progress, or it

is in the Erase Suspend. Besides the I/O6 toggle bit, the

A29002 has a second toggle bit, I/O2, to indicate whether

the addressed sector is being selected for erase. The

A29002 also offers the ability to program in the Erase

Suspend mode. The standard A29002 offers access times of

55, 70, 90, 120, and 150 ns, allowing high-speed

microprocessors to operate without wait states. To eliminate

bus contention the device has separate chip enable ( CE ),

write enable ( WE ) and output enable ( OE ) controls.

n Typical 100,000 program/erase cycles per sector

n 20-year data retention at 125°C

- Reliable operation for the life of the system

n Compatible with JEDEC-standards

- Pinout and software compatible with single-power-

supply Flash memory standard

- Superior inadvertent write protection

n Data Polling and toggle bits

- Provides a software method of detecting completion

of program or erase operations

n Erase Suspend/Erase Resume

- Suspends a sector erase operation to read data

from, or program data to, a non-erasing sector, then

resumes the erase operation

n Hardware reset pin (RESET )

- Hardware method to reset the device to reading

array data (not available on A290021)

n Package options

- 32-pin P-DIP, PLCC, or TSOP(Forward type)

The device requires only a single 5.0 volt power supply for

both read and write functions. Internally generated and

regulated voltages are provided for the program and erase

operations.

The A29002 is entirely software command set compatible

with the JEDEC single-power-supply Flash standard.

Commands are written to the command register using

standard microprocessor write timings. Register contents

serve as input to an internal state-machine that controls the

erase and programming circuitry. Write cycles also

internally latch addresses and data needed for the

programming and erase operations. Reading data out of the

device is similar to reading from other Flash or EPROM

devices.

Device programming occurs by writing the proper program

command sequence. This initiates the Embedded Program

algorithm - an internal algorithm that automatically times the

program pulse widths and verifies proper program margin.

Device erasure occurs by executing the proper erase

command sequence. This initiates the Embedded Erase

algorithm - an internal algorithm that automatically

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper erase margin.

PRELIMINARY (June, 2000, Version 0.2)

1

AMIC Technology, Inc.

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