AM53CF96JC 查看數據表（PDF） - Advanced Micro Devices

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AM53CF96JC

Enhanced SCSI-2 Controller (ESC)

Advanced Micro Devices 

AMD

PRELIMINARY

parity error. This command facilitates data recovery and

thereby minimizes the need to re-transmit data.

AMD’s exclusive power-down feature can be enabled to

help reduce power consumption during the chip’s sleep

mode. The receivers on the SCSI bus may be turned off

to eliminate current that may flow because termination

power (~3 V) is close to the trip point of the input buffers.

The patented GLITCH EATER Circuitry in the

Enhanced SCSI-2 Controller can be programmed to

filter glitches with widths up to 35 ns. It is designed to

dramatically increase system reliability by detecting and

removing glitches that may cause system failure. The

GLITCH EATER Circuitry is implemented on the ACK

and REQ lines since they are most susceptible to

electrical anomalies such as reflections and voltage

spikes. Such signal inconsistencies can trigger false

REQ/ACK handshaking, false data transfers, addition of

random data, and double clocking. AMD’s GLITCH

EATER Circuitry therefore maintains system perform-

ance and improves reliability. The following diagram

illustrates this circuit’s operation.

The Am53CF94 is also available in a 3.3 V version.

GLITCH EATER Circuitry in SCSI Environment

SCSI Environment

Device without the

GLITCH EATER Circuit

AMD’s Device with the

GLITCH EATER Circuit

Glitch Window

Note:

The Glitch Window is programmable via Control Register Four (0DH), bits 6 & 7. Window may be set to 35 ns (max). Default

setting is 12 ns (single-ended).

17348B-1

SYSTEM BLOCK DIAGRAM

CPU

DMA

4

Addr

16

8

Data Am53CF94/96

16

DMA

16

9

SCSI Data

9

SCSI Control

Memory

16

17348B-2

2

Am53CF94/Am53CF96

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