A64E06161(2004) 查看數據表（PDF） - AMIC Technology

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A64E06161
(Rev.:2004)

1M X 16 Bit Low Voltage Super RAM

AMIC Technology 

3. Partial Array Refresh (PAR) mode

In this mode, customers can turn off section of A64E06161 in

stand-by mode to save standby current. The A64E06161 is

divided into four 4M sections allowing certain section to be

active. The array partition to be refreshed is determined by

the respective bit in the CR register. When ZZ is active low,

only the portion of the array that is set in the CR register is

refreshed and the data is keep at a certain section of

memory. The Partial Array Refresh (PAR) mode is only

available during standby time ( ZZ low). Once ZZ is turned

A64E06161

high, the A64E06161 goes back to operating in full array

refresh. For Partial Array Refresh (PAR) mode to be

activated, the register bit, A4 must be set to a “1” value. To

change the address space of the Partial Array Refresh (PAR)

mode, the CR register must be updated using the CR

register description. If the CR register is not updated after

power on, the A64E06161 will be in its default state and the

whole memory array will be refreshed.

Partial Array Refresh – Entry/Exit

ZZ

CE or

UB / LB

1us

suspend

tCDR

Partial Array Mode/

Deep Power Down Mode

tR

Figure 2: Partial Array refresh – Entry/Exit

Partial Array Mode Timings

Parameter

tZZWE

tCDR

tR

tZZMIN

tZZCE

tZZBE

Description

ZZ LOW to WE LOW

Chip Deselect to ZZ LOW

Operation Recovery Time (Deep Power Down Mode only)

Deep Power Down Mode Time

ZZ LOW to CE LOW

ZZ LOW to UB / LD LOW

Min.

0

10

0

0

Max.

1

200

1

1

Unit

µs

µs

µs

µs

µs

µs

Notes:

1. OE and the data pins are in a “don’t care” state while the device is in Partial Array Mode.

2. All other timing parameters are as shown in the switching characteristics section.

3. tR applies only in the Deep Power Down Mode.

4. Temperature Compensated Refresh (TCR) mode

In this mode, the hidden refresh rate can be optimized for the

operating temperature. At higher temperature, the DRAM cell

must be refreshed more often than at lower temperature. By

setting the temperature of operation in CR register, the

refresh rate can be optimized to meet the low standby

current at given operating temperature. There are four

selections (+15°C, +45°C, +70°C, +85°C) in the CR register

description.

PRELIMINARY (November, 2004, Version 0.1)

10

AMIC Technology, Corp.

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