A83516 查看數據表（PDF） - AMIC Technology
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A83516 Datasheet PDF : 12 Pages
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AC Characteristics (TA = -25°C to + 85°C, VCC = 5V ± 10%)
Symbol
Parameter
Program Memory Cycle
tAP
ALE Pulse Width
tALS
Address Valid to ALE Low
tALH
Address Hold from ALE Low
top
PSEN Pulse Width
tAO
ALE Low to PSEN Low
tOI2
PSEN Low to Valid Instruction in
tIDO
Input Instruction Hold after PSEN High
tIFO
Input Instruction Float after PSEN High
External Clock
fOPER
tCK3
tCKH4
tCKL4
Clock Frequency
Clock Period
Clock High Time
Clock Low Time
Data Memory Cycle
tPR
RD Pulse Width
tPD
RD Low to Valid Data in
tDHR
Data Hold from RD High
tDFR
Data Float from RD High
tAR
ALE Low to RD Low
tWP
WR Pulse Width
tDS
Valid Data to WR Low
tDHW
Data Hold from WR High
tAW
ALE Low to WR Low
Serial Port Cycle
tSCK
Serial Port Clock
tKI
Clock Rising Edge to Valid Input Data
tIKH
Input Data to Serial Clock Rising Clock Hold Time
tOKS
Output Data to Serial Clock Rising Edge Setup Time
tOKH
Output Data to Serial Clock Rising Edge Hold Time
1. This 20 ns is due to buffer driving delay and wire loading.
2. Instruction cycle time is 12 tck.
3. tck = 1/ foper
4. There are no duty cycle requirements on the XTAL1 input.
Min.
2tck – 201
1tck
1tck
3tck - 201
1tck
-
-
-
0
25
10
10
6tck - 201
-
0
0
3tck
6tck - 201
1tck
1tck
3tck
12tck
-
0
11tck
1tck
A83516 Series
Max.
-
-
-
-
-
2tck
1tck
1tck
40
-
-
-
-
4tck
2tck
2tck
3tck + 201
-
-
-
3tck + 201
-
11tck
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
MHZ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PRELIMINARY (November, 1998, Version 0.0)
6
AMIC Technology, Inc.
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