AD7008/PCB 查看數據表（PDF） - Analog Devices
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AD7008/PCB Datasheet PDF : 16 Pages
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AD7008
cillator application is with the AD607 Monoceiver(tm). This
unique two chip combination provides a complete receiver sub-
system with digital frequency control, RSSI and demodulated
outputs for AM, FM and complex I/Q (SSB or QAM). (See
Figure 13.)
Direct Digital Modulator
In addition to the basic DDS function provided by the AD7008,
the device also offers several modulation capabilities useful in a
wide variety of application. The simplest modulation scheme is
frequency shift keying or FSK. In this application, each of the
two frequency registers is loaded with a different value, one rep-
resenting the space frequency and the other the mark frequency.
The digital data stream is fed to the FSELECT pin causing
the AD7008 to modulate the carrier frequency between the two
values.
1
1
0
0
0
F SELECT
CLOCK
FREQ 0 32
REG
FREQ 1 32
REG
32
32
MUX
PHASE
ACCUMULATOR
AD7008
Figure 14. FSK Modulator
The AD7008 has three registers that can be used for modula-
tion. Besides the example of frequency modulation shown
above, the frequency registers can be updated dynamically as
can the phase register and the IQMOD register. These can be
modulated at rates up to 16.5 MHz. The example shown below
along with code fragment shows how to implement the AD7008
in an amplitude modulation scheme. Other modulation
schemes can be implemented in a similar fashion.
DSP:
SCALE
ANALOG
ADC INPUT TO
FULL
SCALE
I MOD
10
SIN 10
SIN/COS
ROM
10
COS
10
IOUT
10
10-BIT DAC
10
IOUT
10
10
0
Q MOD
AD7008
Figure 15. Amplitude Modulation
{__________IRQ3 Interrupt Vector__________}
{in_audio is a port used to sample the audio
signal. This signal is assumed to be twos
complement. This interrupt should be serviced
at an audio sample rate. This routine assumes
that the AD7008 has been set up with the Ampli-
tude Modulation Enabled.}
irq3_asserted:
{Get audio sample}
r6=dm(in_audio);
{This section converts the twos complement au-
dio into offset binary scaled for modulating
the AD7008. If twos complement is used, the
modulation scheme will instead be double side-
band, suppressed carrier.}
r5 = 0x80000000;
r6 = r6 xor r5;
r6 = lshift r6 by -1;
r6 = r6 xor r5;
r4 = lshift r6 by -6;
{Load parallel assembly register with modula-
tion data. Q portion set to midscale, I
portion with scaled data}
r5 = 0x00000004;
dm(dds_para) = r5;
dm(dds_para) = r4;
{Transfer parallel assembly register to IQMOD
register}
r4 = 0xb0000000;
dm(dds_cont) = r4;
rti;
Many applications require precise control of the output ampli-
tude, such as in local oscillators, signal generators and modula-
tors. There are several methods to control signal amplitude.
The most direct is to program the amplitude using the IQMOD
register on the AD7008. Other methods include selecting the
load resistor value or changing the value of RSET. Another op-
tion is to place a voltage out DAC on the ground side of RSET as
in Figure 16. This allows easy control of the output amplitude
without affecting other functions of the AD7008. Any combina-
tion of these techniques may be used as long as the full-scale
voltage developed across the load does not exceed 1 volt.
DMDXX–DATA BITS
DMAXX–ADDRESS BITS
U1
74HC138
+5V
DMS1
DMWR
6
4
5
G1
G2A
G2B
DMA02
DMA01
DMA00
3
2
1
C
B
A
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
7
9
10
11
12
13
14
15
DMD24
DMD25
DMD26
DMD27
DMD28
DMD29
DMD30
DMD31
DMD32
DMD33
DMD34
DMD35
DMD36
DMD37
DMD38
DMD39
DMS3
DMD36
DMD37
DMD38
DMD39
+5V
U2
14 50MHz
VCC
RESET
8
OUT
VEE
7 K1115
U3
AD7008
C1
19 D0
20 D1
21 D2
VREF
6
0.1µF
+5V
C2
5
+5V
22 D3
23 D4
24 D5
COMP
0.1µF
2 R4
25 D6
26 D7
IOUT 49.9
1
8 D8
R3
9 D9
IOUT
49.9
10 D10
11 D11
12 D12
13 D13
14 D14
FSADJUST 4
R5
390
15 D15
16 WR
27
32
33
34
35
36
41
42
31
30
38
37
CS
TC0
TC1
TC2
TC3
LOAD
SCLK
SDATA
FSELECT
CLK
RESET
SLEEP
VAA 3 +5V
VDD 17 +5V
VDD
VDD
28
39
+5V
+5V
AGND
DGND
44
7
18
DGND
DGND
DGND
29
43
TEST 40
VOLTAGE OUT DAC,
i.e., AD7245A
0 TO +1 VOLTS
Ifs = 6233 x (VREF –VDAC)
RSET
Figure 16. External Gain Adjustment
REV. B
–11–
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