AD7008/PCB 查看數據表（PDF） - Analog Devices
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AD7008/PCB Datasheet PDF : 16 Pages
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AD7008
TIMING CHARACTERISTICS (VAA = VDD +5 V ± 5%; TA = TMIN to TMAX, unless otherwise noted)
Parameter
AD7008AP20
Min Typ Max
AD7008JP50
Min Typ Max
Units
Test Conditions/Comments
t1
50
20
t2
20
8
t3
20
8
t4
5
5
t5
3
3
t6
4t1
4t1
t7
2t1
2t1
t8
5
5
t9
5
5
t10
10
10
t11
10
10
t12
20
20
t13
10
10
t14
3
3
t15
3
3
t16
20
20
t17
8
8
t18
8
8
t19
10
10
t20
10
10
ns
CLOCK Period
ns
CLOCK High Duration
ns
CLOCK Low Duration
ns
CLOCK to Control Setup Time
ns
CLOCK to Control Hold Time
ns
LOAD Period
ns
LOAD High Duration1
ns
LOAD High to TC0–TC3 Setup Time
ns
LOAD High to TC0–TC3 Hold Time
ns
WR Falling to CS Low Setup Time
ns
WR Falling to CS Low Hold Time
ns
Minimum WR Low Duration
ns
Minimum WR High Duration
ns
WR to D0–D15 Setup Time
ns
WR to D0–D15 Hold Time
ns
SCLK Period
ns
SCLK High Duration
ns
SCLK Low Duration
ns
SCLK Rising to SDATA Setup Time
ns
SCLK Rising to SDATA Hold Time
NOTE
1May be reduced to 1t1 if LOAD is synchronized to CLOCK and Setup (t4) and Hold (t5) Times for LOAD to CLOCK are observed.
CLOCK
FSEL, LOAD,
TC3–TC0
t1
t2
t4
VALID
t5
t3
VALID
Figure 1. Clock Synchronization Timing
LOAD
TC0–TC3
t6
t7
t8
t9
VALID
Figure 2. Register Transfer Timing
CS
WR
D0–D15
t10
t11
t12
t13
t14
t15
VALID DATA
Figure 3. Parallel Port Timing
SCLK
SDATA
t16
t17
t20
t19
DB31
t18
DB0
Figure 4. Serial Port Timing
REV. B
–3–
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