EVAL-AD7482CB 查看數據表（PDF） - Analog Devices

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EVAL-AD7482CB

3 MSPS, 12-Bit SAR ADC

Analog Devices 

AD7482

CIRCUIT DESCRIPTION

CONVERTER OPERATION

The AD7482 is a 12-bit algorithmic successive-approximation

analog-to-digital converter based around a capacitive DAC. It

provides the user with track-and-hold, reference, an A/D con-

verter, and versatile interface logic functions on a single chip.

The normal analog input signal range that the AD7482 can

convert is 0 V to 2.5 V. By using the offset and overrange fea-

tures on the ADC, the AD7482 can convert analog input signals

from –200 mV to +2.7 V while operating from a single 5 V

supply. The part requires a 2.5 V reference, which can be

provided from the part’s own internal reference or an exter-

nal reference source. Figure 3 shows a very simplified

schematic of the ADC. The control logic, SAR, and capaci-

tive DAC are used to add and subtract fixed amounts of

charge from the sampling capacitor to bring the comparator

back to a balanced condition.

CAPACITIVE

DAC

COMPARATOR

CAPACITIVE

DAC

A

VIN

SW1 B

SW2

+

–

COMPARATOR

CONTROL LOGIC

AGND

Figure 5. ADC Acquisition Phase

ADC TRANSFER FUNCTION

The output coding of the AD7482 is straight binary. The designed

code transitions occur midway between the successive integer

LSB values (i.e., 1/2 LSB, 3/2 LSB, and so on). The LSB size

is VREF/4096. The nominal transfer characteristic for the AD7482

is shown in Figure 6. This transfer characteristic may be shifted

as detailed in the Offset/Overrange section.

VIN

VREF

SWITCHES

SAR

111...111

111...110

111...000

011...111

1LSB = V REF/4096

CONTROL

INPUTS

CONTROL

LOGIC

OUTPUT DATA

12-BIT PARALLEL

Figure 3. Simplified Block Diagram of AD7482

Conversion is initiated on the AD7482 by pulsing the CONVST

input. On the falling edge of CONVST, the track-and-hold

goes from track mode to hold mode and the conversion

sequence is started. Conversion time for the part is 300 ns.

Figure 4 shows the ADC during conversion. When conversion

starts, SW2 will open and SW1 will move to Position B, causing

the comparator to become unbalanced. The ADC then runs

through its successive-approximation routine and brings the

comparator back into a balanced condition. When the compara-

tor is rebalanced, the conversion result is available in the

SAR Register.

CAPACITIVE

DAC

A

VIN

SW1 B

SW2

+

–

COMPARATOR

CONTROL LOGIC

000...010

000...001

000...000

0V 0.5LSB

+VREF – 1.5LSB

ANALOG INPUT

Figure 6. AD7482 Transfer Characteristic

POWER SAVING

The AD7482 uses advanced design techniques to achieve very

low power dissipation at high throughput rates. In addition to

this, the AD7482 features two power saving modes, NAP and

Standby. These modes are selected by bringing either the NAP or

STBY Pin to a logic high, respectively.

When operating the AD7482 in normal fully powered mode, the

current consumption is 18 mA during conversion and the quies-

cent current is 12 mA. Operating at a throughput rate of 1 MSPS,

the conversion time of 300 ns contributes 27 mW to the overall

power dissipation.

(300 ns/1 µs) × (5V × 18 mA) = 27 mW

For the remaining 700 ns of the cycle, the AD7482 dissipates

42 mW of power.

(700 ns/1 µs) × (5V × 12 mA) = 42 mW

AGND

Figure 4. ADC Conversion Phase

At the end of conversion, the track-and-hold returns to track mode

and the acquisition time begins. The track-and-hold acquisition

time is 40 ns. Figure 5 shows the ADC during its acquisition

phase. SW2 is closed and SW1 is in Position A. The comparator

is held in a balanced condition and the sampling capacitor

acquires the signal on VIN.

REV. 0

–9–

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