ADMC300 查看數據表（PDF） - Analog Devices
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ADMC300 Datasheet PDF : 42 Pages
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ADMC300–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS (VDD = AVDD = 5 V ؎ 10%, GND = AGND = 0 V, TAMB = –40؇C to +85؇C,
CLKIN = 12.5 MHz, unless otherwise noted)
Parameter
VDD
AVDD
TAMB
Digital Supply Voltage
Analog Supply Voltage
Ambient Operating Temperature
ELECTRICAL CHARACTERISTICS
B Grade
Min
Max
4.50
5.50
4.50
5.50
–40
+85
Units
V
V
°C
Parameter
Test Conditions
Min
Max
Unit
VIH
Hi-Level Input Voltage1, 2
VIL
Lo-Level Input Voltage1, 2
@ VDD = Max
@ VDD = Min
2.0
V
0.8
V
VOH
Hi-Level Output Voltage1, 3
@ VDD = Min,
2.4
V
IOH = –1.0 mA
@ VDD = Min,
VDD – 0.3
V
VOL
Lo-Level Output Voltage1, 3
IOH = –0.1 mA
@ VDD = Min,
0.4
V
IIH
Hi-Level Input Current4
IOL = 2.0 mA
@ VDD = Max,
10
µA
VIN = VDD Max
IIH
Hi-Level PWMTRIP, PIO0–PIO11 Current
@ VDD = Max,
100
µA
VIN = VDD Max
IIH
Hi-Level PWMPOL Current
@ VDD = Max,
10
µA
IIL
Lo-Level Input Current4
VIN = VDD Max
@ VDD = Max,
10
µA
VIN = 0 V
IIL
Lo-Level PWMTRIP, PIO0–PIO11 Current
@ VDD = Max,
10
µA
VIN = 0 V
IIL
Lo-Level PWMPOL Current
@ VDD = Max,
100
µA
IOZH
Hi-Level Three-State Leakage Current5
VIN = 0 V
@ VDD = Max,
10
µA
IOZL
Lo-Level Three-State Leakage Current5
VIN = VDD Max
@ VDD = Max,
10
µA
VIN = 0 V
IDD
Digital Power Supply Current (Dynamic)6, 7
@ VDD = Max
IDD
Analog Power Supply Current (Disabled)8
@ AVDD = VDD = Max
100
mA
100
µA
IDD
Analog Power Supply Current (Ref Only)
@ AVDD = VDD = Max
6.5
mA
IDD
Analog Power Supply Current (Ref + BankA)
@ AVDD = VDD = Max
11.0
mA
IDD
Analog Power Supply Current (Ref + BankB)
@ AVDD = VDD = Max
13.0
mA
IDD
Analog Power Supply Current (Ref + BankA/B) @ AVDD = VDD = Max
18.0
mA
NOTES
1Bidirectional pins: PIO0–PIO11, RFS0, RFS1, TFS0, TFS1, SCLK0, SCLK1.
2Input only pins: PWMTRIP, PWMPOL, RESET, EIA, EIB, EIZP, DR1A, DR1B, DR0, CLKIN.
3Output pins: PWMSYNC, CL, CH, BL, BH, AL, AH, MUX0–MUX2, AUX0, AUX1, CLKOUT, DT0, DT1.
4Input only pins: RESET, EIA, EIB, EIZP, DR1A, DR1B, DR0, CLKIN.
5Three-stateable pins: DT0, DT1, RFS0, RFS1, TFS0, TFS1, SCLK0, SCLK1.
6Current reflects device operating with no output loads.
7Dynamic condition refers to continuous operation of the DSP core, ADC banks and PWM generation in single update mode with PWMTM = 0x0480, ADCDIVA =
ADCDIVB = 0x180. The encoder inputs are quiescent.
8Disabled refers to powering down both ADC banks and the internal reference generation circuit by setting Bits 10, 11 and 12 of the ADCCTRL register. Current is
total current from AVDD supply.
Specifications subject to change without notice.
–2–
REV. B
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