ADT7468ARQ-REEL7 查看數據表（PDF） - Analog Devices
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ADT7468ARQ-REEL7 Datasheet PDF : 80 Pages
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ADT7468
Parameter
Min
OPEN-DRAIN DIGITAL OUTPUTS, PWM1 TO PWM3, XTO
Current Sink, IOL
Output Low Voltage, VOL
High Level Output Current, IOH
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, VOL
High Level Output Current, IOH
SMBUS DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH
2.0
Input Low Voltage, VIL
Hysteresis
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, VIH
2.0
Input Low Voltage, VIL
−0.3
Hysteresis
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, VIH
Input Low Voltage, VIL
DIGITAL INPUT CURRENT
Input High Current, IIH
−1
Input Low Current, IIL
Input Capacitance, CIN
SERIAL BUS TIMING
Clock Frequency, fSCLK
10
Glitch Immunity, tSW
Bus Free Time, tBUF
4.7
Start Setup Time, tSU;STA
4.7
Start Hold Time, tHD;STA
4.0
SCL Low Time, tLOW
4.7
SCL High Time, tHIGH
4.0
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Data Setup Time, tSU;DAT
250
Data Hold Time, tHD;DAT
300
Detect Clock Low Timeout, tTIMEOUT
15
Typ
Max
8.0
0.4
0.1
1.0
0.4
0.1
1.0
0.4
500
5.5
0.8
0.5
0.75 × VCCP
0.4
1
5
400
50
50
1000
300
35
Unit Test Conditions/Comments
mA
V
IOUT = −8.0 mA, VCC = +3.3 V
µA
VOUT = VCC
V
IOUT = −4.0 mA, VCC = +3.3 V
µA
VOUT = VCC
V
V
mV
V
V
V
V
V p-p
Maximum input voltage
Minimum input voltage
V
V
µA
VIN = VCC
µA
VIN = 0
pF
See Figure 2
kHz
ns
µs
µs
µs
µs
µs
ns
µs
ns
ns
ms Can be optionally disabled
SCL
tR
tLOW
tHD; STA
SDA
tBUF
P
S
tHD; DAT
tF
tHIGH
tSU; DAT
tHD; STA
tSU; STA
S
Figure 2. Serial Bus Timing Diagram
tSU; STO
P
Rev. 0 | Page 4 of 80
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