ADUC812(1999) 查看數據表（PDF） - Analog Devices

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ADUC812
(Rev.:1999)

MicroConverter™, Multichannel 12-Bit ADC with Embedded FLASH MCU

Analog Devices 

ADuC812

The program memory array can be programmed in one of two

modes, namely:

Serial Downloading (In-Circuit Programming)

As part of its factory boot code, the ADuC812 facilitates serial

code download via the standard UART serial port. Serial down-

load mode is automatically entered on power-up if the external

pin, PSEN, is pulled low through an external resistor as shown

in Figure 9. Once in this mode, the user can download code to

the program memory array while the device is sited in its target

application hardware. A PC serial download executable is pro-

vided as part of the ADuC812 QuickStart development system.

The Serial Download protocol is detailed in a MicroConverter

Applications Note available from ADI.

+5V

PROGRAM MODE

(SEE TABLE V)

VDD

P0

GND

ADuC812

P3

P1

GND

VDD

PSEN

RST

XTAL1

P2

ALE

XTAL2

PROGRAM

DATA

(D0–D7)

PROGRAM

ADDRESS

(A0–A13)

(P2.0 = A0)

(P1.7 = A13)

WRITE ENABLE

STROBE

Figure 10. Flash/EE Memory Parallel Programming

Table V shows the normal parallel programming modes that can

be configured using Port 3 bits.

ADuC812

PSEN

PULL PSEN LOW DURING RESET TO

CONFIGURE THE ADuC812

FOR SERIAL DOWNLOAD MODE

1k⍀

Figure 9. Flash/EE Memory Serial Download Mode

Programming

Parallel Programming

The parallel programming mode is fully compatible with con-

ventional third party Flash or EEPROM device programmers. A

block diagram of the external pin configuration required to

support parallel programming is shown in Figure 10. In this

mode Ports P0, P1 and P2 operate as the external data and

address bus interface, ALE operates as the Write Enable strobe

and Port P3 is used as a general configuration port that config-

ures the device for various program and erase operations during

parallel programming. The high voltage (12 V) supply required

for Flash programming is generated using on-chip charge pumps

to supply the high voltage program lines.

Table V. Flash Memory Parallel Programing Modes

Port Pins (P3.0–P3.7)

.7 .6 .5 .4 .3 .2 .1 .0 Programming Mode

1 X X X 0 0 0 1 Erase Flash Program

Erase Flash User

1 X X X 0 0 1 1 Read Manufacture and

Chip ID

1 X X X 0 1 0 1 Program Byte

1 X X X 0 1 1 1 Read Byte

1 X X X 1 0 0 1 Reserved

1 X X X 1 0 1 1 Reserved

Any Other Code

Redundant

Using the Flash/EE Data Memory

The user Flash/EE data memory array consists of 640 bytes that

are configured into 160 (00H to 9FH), 4-byte pages as shown in

Figure 11.

9FH BYTE 1 BYTE 2

BYTE 3

BYTE 4

00H BYTE 1 BYTE 2

BYTE 3

BYTE 4

Figure 11. User Flash/EE Memory Configuration

As with other user peripherals the interface to this memory

space is via a group of registers mapped in the SFR space. A

group of four data registers (EDATA1-4) are used to hold the

4-byte page data just accessed. EADRL is used to hold the 8-bit

address of the page to be accessed. Finally, ECON is an 8-bit

control register that may be written with one of five Flash/EE

memory access commands to enable various read, write, erase

and verify modes.

REV. 0

–13–

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