ADUC812(1999) 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
生产厂家
ADUC812 Datasheet PDF : 31 Pages
| |||
ADuC812
ADCCON1 ADC CONTROL REGISTER #1
ADCCON1.7 ADC POWER CONTROL BITS
ADCCON1.6 [SHTDN, NORM, AUTOSHTDN,
AUTOSTBY]
ADCCON1.5 CONVERSION TIME = 16/ADCCLK
ADCCON1.4 ADCCLK = MCLK/[1, 2, 4, 8]
ADCCON1.3 ACQUISITION TIME SELECT BITS
ADCCON1.2 ACQ TIME = [1, 2, 3, 4]/ADCCLK
ADCCON1.1 TIMER2 CONVERT ENABLE
ADCCON1.0 EXTERNAL CONVST ENABLE
ADCCON2 ADC CONTROL REGISTER #2
ADCI
DMA
CCONV
SCONV
CS3
CS2
CS1
CS0
ADC INTERRUPT FLAG
DMA MODE ENABLE
CONTINUOUS CONVERSION ENABLE BIT
SINGLE CONVERSION START BIT
INPUT CHANNEL SELECT BITS
0000–0111 = ADC0–ADC7
1XXX = TEMPERATURE SENSOR
1111 = "HALT" COMMAND
(IN DMA MODE ONLY)
ADCCON3
ADC CONTROL REGISTER #3
ADCCON3.7 BUSY INDICATOR FLAG
(0 = ADC NOT ACTIVE)
ADCCON3.6 THIS BIT MUST CONTAIN ZERO
ADCCON3.5 THIS BIT MUST CONTAIN ZERO
ADCCON3.4 THIS BIT MUST CONTAIN ZERO
ADCCON3.3 THIS BIT MUST CONTAIN ZERO
ADCCON3.2 THIS BIT MUST CONTAIN ZERO
ADCCON3.1 THIS BIT MUST CONTAIN ZERO
ADCCON3.0 THIS BIT MUST CONTAIN ZERO
ADCDATAH
ADCDATAL
ADC DATA REGISTERS
DMAP, DMAH, DMAL DMA ADDRESS POINTER
ADCGAINH ADC GAIN
ADCGAINL CALIBRATION COEFFICIENTS
ADCOFSH ADC OFFSET
ADCOFSL CALIBRATION COEFFICIENTS
DACCON
DACCON.7
DACCON.6
DACCON.5
DACCON.4
DACCON.3
DACCON.2
DACCON.1
DACCON.0
DAC CONTROL REGISTER
MODESELECT (0 = 12 BIT, 1 = 8 BIT)
DAC1 RANGE SELECT (0 = VREF, 1 = VDD)
DAC0 RANGE SELECT (0 = VREF, 1 = VDD)
CLEAR DAC1
(0 = 0V, 1 = NORMAL OPERATION)
CLEAR DAC0
(0 = 0V, 1 = NORMAL OPERATION)
SYNCHRONOUS UPDATE
(1 = ASYNCHRONOUS)
POWERDOWN DAC1 (0 = OFF, 1 = ON)
POWERDOWN DAC0 (0 = OFF, 1 = ON)
DAC1H, DAC1L DAC1 DATA REGISTERS
DAC0H, DAC0L DAC0 DATA REGISTERS
Figure 17. ADC and DAC—Control and Configuration SFRs
P0
P1
T2EX
T2
P2
PORT0 REGISTER (ALSO A0–A7 & D0–D7)
PORT1 REGISTER (ANALOG & DIGITAL INPUTS)
TIMER/COUNTER 2 CAPTURE/RELOAD TRIGGER
TIMER/COUNTER 2 EXTERNAL INPUT
PORT2 REGISTER (ALSO A8–A15 & A16–A23)
P3
RD
WR
T1
T0
INT1
INT0
TxD
RxD
PORT3 REGISTER
EXTERNAL DATA MEMORY READ STROBE
EXTERNAL DATA MEMORY WRITE STROBE
TIMER/COUNTER 1 EXTERNAL INPUT
TIMER/COUNTER 0 EXTERNAL INPUT
EXTERNAL INTERRUPT 1
EXTERNAL INTERRUPT 0
SERIAL PORT TRANSMIT DATA LINE
SERIAL PORT RECEIVE DATA LINE
SCON SERIAL COMMUNICATIONS CONTROL REGISTER
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
UART MODE CONTROL BITS BAUD RATE:
00 - 8 BIT SHIFT REGISTER FOSC/12
01 - 8 BIT UART
TIMER OVERFLOW
RATE/32 (؋2)
10 - 9 BIT UART
11 - 9 BIT UART
FOSC/64 (؋2)
TIMER OVERFLOW
RATE/32 (؋2)
IN MODES 2&3, ENABLES MULTIPROCESSOR
COMMUNICATION
RECEIVE ENABLE CONTROL BIT
IN MODES 2&3, 9TH BIT TRANSMITTED
IN MODES 2&3, 9TH BIT RECEIVED
TRANSMIT INTERRUPT FLAG
RECEIVE INTERRUPT FLAG
SBUF SERIAL PORT BUFFER REGISTER
PCON
PCON.7
PCON.4
PCON.3
PCON.2
PCON.1
PCON.0
POWER CONTROL REGISTER
DOUBLE BAUD RATE CONTROL
ALE DISABLE
(0 = NORMAL, 1 = FORCES ALE HIGH)
GENERAL PURPOSE FLAG
GENERAL PURPOSE FLAG
POWER-DOWN CONTROL BIT
(RECOVERABLE WITH HARD RESET)
IDLE-MODE CONTROL
(RECOVERABLE WITH ENABLED
INTERRUPT)
PSW
CY
AC
F0
RS1
RS0
OV
F1
P
DPP
PROGRAM STATUS WORD
CARRY FLAG
AUXILIARY CARRY FLAG
GENERAL PURPOSE FLAG 0
REGISTER BANK SELECT
CONTROL BITS
ACTIVE REGISTER BANK = [0, 1, 2, 3]
OVERFLOW FLAG
GENERAL PURPOSE FLAG 1
PARITY OF ACC
DATA POINTER PAGE
DPH, DPL (DPTR) DATA POINTER
ACC ACCUMULATOR
B
SP
STACK POINTER
WDCON WATCHDOG TIME
CONTROL REGISTER
PRE2 WATCHDOG TIMEOUT SELECTION BITS
PRE1 TIMEOUT = [16, 32, 64, 128, 256, 512, 1024,
PRE0 2048] ms
WDR1 WATCHDOG TIMER REFRESH BITS
WDR2 SET SEQUENTIALLY TO REFRESH
WATCHDOG
WDS WATCHDOG STATUS FLAG
WDE WATCHDOG ENABLE
PSMCON POWER SUPPLY MONITOR
CONTROL REGISTER
PSMCON.7
PSMCON.6
PSMCON.5
PSMCON.4
PSMCON.3
PSMCON.2
PSMCON.1
PSMCON.0
(NOT USED)
PSM STATUS BIT
(1 = NORMAL/0 = FAULT)
PSM INTERRUPT BIT
TRIP POINT SELECT BITS
[4.63V, 4.37V, 3.08V, 2.93V, 2.63V]
AVDD/DVDD FAULT INDICATOR
(1 = ADD/0 = DVDD)
PSM POWERDOWN CONTROL
(1 = ON/0 = OFF)
ECON DATA FLASH MEMORY
COMMAND REGISTER
01h READ
04h VERIFY
02h WRITE
05h ERASE
03h (RESERVED) 06h ERASE ALL
EADRL DATA FLASH MEMORY
ADDRESS REGISTER
EDATA1, EDATA2, EDATA3, EDATA4
DATA FLASH DATA REGISTERS
ETIM1, ETIM2, ETIM3
FLASH TIMING REGISTERS
Figure 18. 8051 Core, On-Chip Monitors and Flash/EE Data Memory SFRs
REV. 0
–19–
Share Link: 