ADUC814ARU(Rev0) 查看數據表（PDF） - Analog Devices

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ADUC814ARU
(Rev.:Rev0)

MicroConverter®, Small Package 12-Bit ADC with Embedded FLASH MCU

Analog Devices 

ADuC814

TIMING SPECIFICATIONS1, 2, 3 (AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; all

specifications TMIN to TMAX, unless otherwise noted.)

Parameter

32.768 kHz External Crystal

Min

Typ

Max

Unit

Figure

CLOCK INPUT (External Clock Driven XTAL1)

tCK

tCKL

tCKH

tCKR

tCKF

1/tCORE

tCORE

tCYC

XTAL1 Period

XTAL1 Width Low

XTAL1 Width High

XTAL1 Rise Time

XTAL1 Fall Time

ADuC814 Core Clock Frequency4

ADuC814 Core Clock Period5

ADuC814 Machine Cycle Time6

0.131

0.72

30.52

15.16

15.16

20

20

0.476

5.7

16.78

91.55

µs

1

µs

1

µs

1

ns

1

ns

1

MHz

µs

µs

NOTES

1AC inputs during testing are driven at DVDD – 0.5 V for a Logic 1 and 0.45 V for a Logic 0. Timing measurements are made at VIH min for a Logic 1, and VIL max

for a Logic 0, as shown in Figure 2.

2For timing purposes, a port pin is no longer floating when a 100 mV change from the load voltage occurs. A port pin begins to float when a 100 mV change from the

loaded VOH/VOL level occurs, as shown in Figure 2.

3CLOAD for all outputs = 80 pF, unless otherwise noted.

4ADuC814 internal PLL locks onto a multiple 512 times the external crystal frequency of 32.768 kHz to provide a stable 16.777216 MHz internal clock for the

system. The core can operate at this frequency or at a binary submultiple called Core_CLK, selected via the PLLCON SFR.

5This number is measured at the default Core_CLK operating frequency of 2.09 MHz.

6ADuC814 machine cycle time is nominally defined as 12/Core_CLK.

tCKH

tCKR

tCKL

tCKF

tCK

Figure 1. XTAL1 Input

DVDD – 0.5V

0.45V

0.2DVDD + 0.9V

TEST POINTS

0.2DVDD – 0.1V

VLOAD – 0.1V

VLOAD

VLOAD + 0.1V

TIMING

REFERENCE

POINTS

Figure 2. Timing Waveform Characteristics

VLOAD – 0.1V

VLOAD

VLOAD + 0.1V

REV. 0

–7–

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