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ADUC814ARU(Rev0) 查看數據表(PDF) - Analog Devices

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ADUC814ARU Datasheet PDF : 16 Pages
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ADuC814
TIMING SPECIFICATIONS (continued)
Parameter
16.78 MHz Core_CLK
Min Typ Max
UART TIMING (Shift Register Mode)
tXLXL
Serial Port Clock Cycle Time
715
tQVXH
tDVXH
tXHDX
Output Data Setup to Clock 463
Input Data Setup to Clock
252
Input Data Hold after Clock 0
tXHQX
Output Data Hold after Clock 22
Variable Core_CLK
Min
Typ
Max
12tCORE
10tCORE – 133
2tCORE + 133
0
2tCORE – 117
Unit Figure
µs 3
ns 3
ns 3
ns 3
ns 3
TXD
(OUTPUT CLOCK)
RXD
(OUTPUT DATA)
RXD
(INPUT DATA)
01
MSB
67
tQVXH
BIT 6
tXHQX
tXLXL
BIT 1
tDVXH
tXHDX
MSB
BIT 6
BIT 1
Figure 3. UART Timing in Shift Register Mode
SET RI
OR
SET TI
LSB
–8–
REV. 0

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