ADUC814ARU(Rev0) 查看數據表（PDF） - Analog Devices
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ADUC814ARU
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
ADUC814ARU Datasheet PDF : 16 Pages
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ADuC814
Parameter
Min
Typ
Max
Unit
SPI MASTER MODE TIMING (CPHA = 1)
tSL
SCLOCK Low Pulsewidth*
tSH
SCLOCK High Pulsewidth*
tDAV
Data Output Valid after SCLOCK Edge
tDSU
Data Input Setup Time before SCLOCK Edge 100
tDHD
tDF
Data Input Hold Time after SCLOCK Edge
100
Data Output Fall Time
tDR
Data Output Rise Time
tSR
SCLOCK Rise Time
tSF
SCLOCK Fall Time
630
ns
630
ns
50
ns
ns
ns
10
25
ns
10
25
ns
10
25
ns
10
25
ns
*Characterized under the following conditions:
a. Core clock divider Bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 2.09 MHz.
b. SPI bit rate selection Bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively.
Figure
4
4
4
4
4
4
4
4
4
SCLOCK
(CPOL = 0)
SCLOCK
(CPOL = 1)
MOSI
MISO
tSH
tSL
tSR
tSF
tDAV
tDF
MSB
tDR
BITS 6–1
LSB
MSB IN
BITS 6–1
tDSU tDHD
Figure 4. SPI Master Mode Timing (CPHA = 1)
LSB IN
REV. 0
–9–
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