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LC723748 查看數據表(PDF) - SANYO -> Panasonic

零件编号
产品描述 (功能)
生产厂家
LC723748
SANYO
SANYO -> Panasonic SANYO
LC723748 Datasheet PDF : 14 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
LC723732/40/48/56/64
Electrical Characteristics in the allowable operating ranges
Parameter
Input high-level current
Input low-level current
Input floating voltage
Hysteresis
Output high-level voltage
Output low-level voltage
Output off leakage current
A/D conversion error
Rejected pulse width
Power down detection voltage
Pull-down resistance
Current drain
Symbol
IIH1
IIH2
IIH3
IIH4
IIL1
IIL2
IIL3
VIF
VH
VOH1
VOH2
VOH3
VOL1
VOL2
VOL3
VOL4
IOFF1
IOFF2
IOFF3
PREJ
VDET
RPD1
RPD2
IDD1
IDD2
IDD3
IDD4
Conditions
min
XIN: VI = VDD = 5.0 V
2.0
FMIN, AMIN, HCTR, LCTR: VI = VDD = 5.0 V
4.0
PA, PB, PC, PD, PE, PF, PG, PH, PI, PK, PL,
PM, PN, PO, PP, PQ, PR, PS, PT-PORT,
SNS, HOLD, RESET, HCTR, LCTR, E03,
SUBPD: VI = VDD = 5.0 V
(With the port PA pull-down resistors disabled,
and PB, PC, PD, PE, PF, PG, PK, PL, PM,
PN, PP, PO, PQ, PR, PS, and PT ports set to
input mode.)
Port PA (pull-down resistors enabled):
VI = VDD = 5.0 V
XIN: VI = VSS
2.0
FMIN, AMIN, HCTR, LCTR: VI = VSS
4.0
PA, PB, PC, PD, PE, PF, PG, PH, PI, PK, PL,
PM, PN, PO, PP, PQ, PR, PS, PT-PORT,
SNS, HOLD, RESET, HCTR, LCTR, E03,
SUBPD: VI = VSS
(With the port PA pull-down resistors disabled,
and PB, PC, PD, PE, PF, PG, PK, PL, PM,
PN, PP, PO, PQ, PR, PS, and PT ports set to
input mode.)
Port PA (pull-down resistors enabled)
PD, PE, PF, PG, PK-PORT, RESET,
LCTR(in period measurement mode)
0.1 VDD
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO,
PP, PQ, PR, PS, PT-PORT: IO = –1 mA
EO1, EO2, EO3, SUBPD: IO = –500 µA
XOUT: IO = –200 µA
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO,
PP, PQ, PR, PS, PT-PORT: IO = 1 mA
E01, E02, E03, SUBPD: IO = 500 µA
XOUT: IO = 200 µA
PC, PJ-PORT: IO = 5 mA
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO,
PP, PQ, PR, PS, PT-PORT
VDD – 1.0
VDD – 1.0
VDD – 1.0
–3.0
E01, E02, E03, SUBPD
–100
PC, PJ-PORT
–5.0
ADI0 to ADI7 VDD1
SNS
–1.5
2.6
Port PA (pull-down resistors enabled):
VDD = 5 V
75
TEST1, TEST2
During normal operation (PLL operating)
VDD1, fIN2 = 130 MHz Ta = 25°C
Halt mode (CPU operation stopped, crystal
oscillator operating) (See figure 1.)
VDD2, Ta = 25°C*
Backup mode (crystal oscillator stopped)
(See figure 2.) VDD = 5.5 V, Ta = 25°C
Backup mode (crystal oscillator stopped)
(See figure 2.) VDD = 2.5 V, Ta = 25°C
Ratings
typ
5.0
10
50
5.0
10
0.2 VDD
3.0
100
10
20
0.45
Note *: Twenty instruction steps are executed every millisecond. The PLL, universal counter, and other functions are stopped.
max
15
30
3.0
15
30
3.0
0.05 VDD
1.0
1.0
1.5
2.0
3.0
100
5.0
1.5
50
3.4
200
30
5
1
Unit
µA
µA
µA
µA
µA
µA
µA
V
V
V
V
V
V
V
V
V
µA
nA
µA
LSB
µsec
V
k
k
mA
mA
µA
µA
No. 5931-6/14

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