LC723748 查看數據表（PDF） - SANYO -> Panasonic
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LC723748 Datasheet PDF : 14 Pages
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LC723732/40/48/56/64
Continued from preceding page.
Pin No. Symbol
I/O
Function
General-purpose I/O ports with shared functions as serial I/O ports
The input formats are Schmitt inputs. The PE1/SCK2 and PE2/SO2 pins can be
16
PE0
switched to function as open drain outputs.
The IOS1 instruction is used to switch between the general-purpose I/O port and
15 PE1/SCK2
serial I/O port functions.
14
PE2/S02
13
PE3/SI2
• When used as general-purpose I/O ports:
The pins are set to the general-purpose I/O port function using the IOS1
instruction.
12
PF0
The mode (input or output) is set in 1-bit units using the IOS1 instruction.
11 PF1/SCK1
• When used as serial I/O ports:
I/O The pins are set to the serial I/O port function using the IOS1 instruction.
10
PF2/S01
[Pin states when set to the serial I/O port function]
9
PF3/SI1
PE0, PF0, PG0 ... General-purpose I/O
8
PG0
7
PG1/SCK0
PE1, PF1, PG1 ... SCK input or output
PE2, PF2, PG2 ... SO output
PE3, PF3, PG3 ... SI input
6
PG2/S00
The PE1/SCK2 and PE2/SO2 pins can be switched to function as open drain
5
PG3/SI0
outputs with the IOS2 instruction. When using this circuit type, the external pull-up
resistors must be connected to the same power supply as that used by the IC.
Input is disabled and the pins go to the high-impedance state in backup mode.
These ports are set up as general-purpose input ports after a power on reset.
Equivalent circuit
1
XIN
I
Connections for a 4.5-MHz crystal oscillator element
100
XOUT
O
Main charge pump outputs
These pins output a high level when the frequency of the local oscillator divided by n
98
E01
is higher than that of the reference frequency, and they output a low level when that
O frequency is lower. They go to the high-impedance state when the frequencies
97
E02
match.
These pins go to the high-impedance state in backup mode, after a power on reset,
and in the PLL stopped state.
39
VDDPORT
Power supply connections
93
VDDPLL
The VDDPORT and VSSPORT pins mainly supply power for the peripheral I/O blocks
and the regulator.
4
40
VSSCPU
VSSPORT
—
The VDDPLL and VSSPLL pins mainly for the PLL circuits.
The VSSCPU pin is mainly used by the CPU block.
81
VSSADC
96
VSSPLL
The VSSADC pin is mainly used by the A/D converter block.
Since all the VDD and VSS pins are independent, all must be connected to the same
power supply.
3
VREG
O
Internal low voltage output
Connect a bypass capacitor to this pin.
FM VCO (local oscillator) input
This pin is selected with CW1 in the PLL instruction.
95
FMIN
I The signal input to this pin must be capacitor coupled.
Input is disabled in backup mode, after a power on reset, and in the PLL stopped
state.
AM VCO (local oscillator) input
This pin is selected and the band set with CW1 (b1, b0) in the PLL instruction.
b1 b0
Band
1
0
2 to 40 MHz (SW)
94
AMIN
I
1
1 0.5 to 10 MHz (MW, LW)
The signal input to this pin must be capacitor coupled.
Input is disabled in backup mode, after a power on reset, and in the PLL stopped
state.
Continued on next page.
No. 5931-8/14
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