AS29LV016 查看數據表（PDF） - Austin Semiconductor

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AS29LV016

16 Megabit (2M x 8-Bit / 1M x 16-Bit) CMOS 3.0 Volt-Only Boot Sector Flash Memory

Austin Semiconductor 

COTS PEM

BOOT SECTOR FLASH

Austin Semiconductor, Inc.

AS29LV016

STANDBY MODE

When the system is not reading or writing to the device,

it can place the device in the standby mode. In this mode,

current consumption is greatly reduced, and the outputs

are placed in the high impedance state, independent of

the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at VCC ± 0.3 V.

(Note that this is a more restricted voltage range than

VIH.) If CE# and RESET# are held at VIH, but not within

VCC ± 0.3 V, the device will be in the standby mode, but

the standby current will be greater. The device requires

standard access time (tCE) for read access when the device

is in either of these standby modes, before it is ready to

read data.

If the device is deselected during erasure or programming,

the device draws active current until the operation is

completed.

ICC3 and ICC4 represents the standby current specification

shown in the table in DC Characteristics on page 27.

AUTOMATIC SLEEP MODE

The automatic sleep mode minimizes Flash device energy

consumption. The device automatically enables this mode

when addresses remain stable for tACC + 30 ns. The

automatic sleep mode is independent of the CE#, WE#,

and OE# control signals. Standard address access timings

provide new data when addresses are changed. While in

sleep mode, output data is latched and always available

to the system. ICC4 in the DC Characteristics on page 27

represents the automatic sleep mode current specification.

RESET#: HARDWARE RESET PIN

The RESET# pin provides a hardware method of resetting

the device to reading array data. When the system drives

the RESET# pin to VIL for at least a period of tRP, the

device immediately terminates any operation in

progress, tristates all data output pins, and ignores all

read/write attempts for the duration of the RESET# pulse.

The device also resets the internal state machine to

reading array data. The operation that was interrupted

should be reinitiated once the device is ready to accept

another command sequence, to ensure data integrity.

Current is reduced for the duration of the RESET# pulse.

When RESET# is held at VSS±0.3 V, the device draws

CMOS standby current (ICC4). If RESET# is held at VIL but

not within VSS±0.3 V, the standby current will be greater.

The RESET# pin may be tied to the system reset circuitry.

A system reset would thus also reset the Flash memory,

enabling the system to read the boot-up firmware from

the Flash memory.

If RESET# is asserted during a program or erase

operation, the RY/BY# pin remains a 0 (busy) until the

internal reset operation is complete, which requires a time

of t (during Embedded Algorithms). The system can

READY

thus monitor RY/BY# to determine whether the reset

operation is complete. If RESET# is asserted when a

program or erase operation is not executing (RY/BY# pin

is 1), the reset operation is completed within a time of

tREADY (not during Embedded Algorithms). The system can

read data tRH after the RESET# pin returns to VIH.Refer to

the tables in AC Characteristics on page 29 for RESET#

parameters and to Figure 13, on page 30 for the timing

diagram.

AS29LV016

Rev. 2.1 10/08

Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.

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