AS4LC4M4883C 查看數據表（PDF） - Austin Semiconductor

零件编号

产品描述 (功能)

生产厂家

AS4LC4M4883C

4 MEG x 4 DRAM 3.3V, EDO PAGE MODE

Austin Semiconductor 

AUSTIN SEMICONDUCTOR, INC.

AS4LC4M4 883C

4 MEG x 4 DRAM

NOTES

1. All voltages referenced to VSS.

2. This parameter is sampled. VCC = +3.3V; f = 1 MHz.

3. ICC is dependent on cycle rates.

4. ICC is dependent on output loading and cycle rates.

Specified values are obtained with minimum cycle

time and the outputs open.

5. Enables on-chip refresh and address counters.

6. The minimum specifications are used only to indicate

cycle time at which proper operation over the ful

temperature range is assured.

7. An initail pause of 100µs is required after power-up

followed by eight /R/A/S refresh cycles (/R/A/S ONLY or

CBR with /W/E HIGH) before proper device operation

is assured. The eight /R/A/S cycle wake-ups should be

repeated any thime the tREF refresh requirement is

exceeded.

8. AC characteristics assume tT = 2.5ns.

9. VIH (MIN) and VIL (MAX) are reference levels for

measuring timing of input signals. Transition times

are measured between VIH and VIL (or between VIL

and VIH).

10. In addition to meeting the transition rate specifica-

tion, all input signals must transit between VIH and

VIL (or between VIL and VIH) in a monotonic manner.

11. Column address changed once each cycle.

12. Measured with a load equivalent to two TTL gates,

100pF and VOL = 0.8V and VOH = 2.0V.

13. Assumes that tRCD < tRCD (MAX). If tRCD is greater

than the maximum recommended value shown in this

table, tRAC will increase by the amount that tRCD

exceeds the value shown.

14. Assumes that tRCD≥ tRCD (MAX).

15. If ?C?A/S is LOW at the falling edge of ?R?A/S, Q will be

maintained from the previous cycle. To initiate a new

cycle and clear the data-out buffer, ?C?A/S must be

pulsed HIGH for tCP.

16. Operation within the tRCD (MAX) limit ensures that

tRAC (MAX) can be met. tRCD (MAX) is specified as

a reference point only; if tRCD is greater than the

specified tRCD (MAX) limit, then access time is

controlled exclusively by tCAC, provided tRAD is not

exceeded.

17. Operation within the tRAD (MAX) limit ensures that

tRAC (MIN) and tCAC (MIN) can be met. tRAD

(MAX) is specified as a reference point only; if tRAD

is greater than the specified tRAD (MAX) limit, then

access time is controlled exclusively by tAA, provided

tRCD is not exceeded.

18. Either tRCH or tRRH must be satisfied for a READ

cycle.

19. tOFF (MAX) defines the time at which the output

achieves the open circuit condition, and is not

referenced to VOH or VOL. It is referenced from the

rising edge of ?R?A/S or ?C?A/S, whichever occurs last.

20. tWCS, tRWD, tAWD and tCWD are not restrictive

operating parameters. tWCS applies to EARLY

WRITE cycles. tRWD, tAWD and tCWD apply to

READ-MODIFY-WRITE cycles. If tWCS ≥ tWCS

(MIN), the cycle is an EARLY WRITE cycle and the

data output will remain an open circuit throughout

the entire cycle. If tWCS < tWCS (MIN) and tRWD ≥

tRWD (MIN), tAWD ≥ tAWD (MIN) and tCWD ≥

tCWD (MIN), the cycle is a READ-MODIFY-WRITE

and the data output will contain data read from the

selected cell. If neither of the above conditions is met,

the state of data-out is indeterminate. ?O/E held HIGH

and ?W/E taken LOW after ?C?A/S goes LOW results in a

LATE WRITE (?O/E-controlled) cycle. tWCS, tRWD,

tCWD and tAWD are not applicable in a LATE

WRITE cycle.

21. These parameters are referenced to ?C?A/S leading edge

in EARLY WRITE cycles and ?W/E leading edge in

LATE WRITE or READ-MODIFY-WRITE cycles.

22. If ?O/E is tied permanently LOW, LATE WRITE or

READ-MODIFY-WRITE operations are not permis-

sible and should not be attempted. Additionally, ?W/E

must be pulsed during ?C?A/S HIGH time in order to

place I/O buffers in High-Z.

23. A HIDDEN REFRESH may also be performed after a

WRITE cycle. In this case, ?W/E = LOW and

?O/E = HIGH.

24. tWTS and tWTH are setup and hold specifications for

the /W/E pin being held LOW to enable the JEDEC test

mode (with CBR timing constraints). These two

parameters are the inverts of tWRP and tWRH in the

CBR REFRESH cycle.

AS4LC4M4

Rev. 11/97

DS000022

2-80

Austin Semiconductor, Inc., reserves the right to change products or specifications without notice.

Share Link: