KGL4202 查看數據表（PDF） - Oki Electric Industry

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KGL4202

10-Gbps GaAs Family High-Speed Optical Communications System

Oki Electric Industry 

10-GHz GaAs Family

High-Speed Optical Communications Systems

INTRODUCTION

Oki’s 10-GHz logic devices are manufactured using a 0.2-µm, ion-implanted process, which is similar to

Oki’s familiar 0.5-µm telecommunications process. However, the 0.2-µm process uses a phase-shifting

edge line (PEL) masking method for gate fabrication. Gold-based, three-level metal interconnections are

used for high density and shorter wiring paths. Layers 1 and 2 are signal lines. Layer 3, which is formed

by electroplating, is used for ground or power supply lines because of its lower resistance. An optional

buried “p” channel structure is adopted for reducing short channel effects.

The following table shows the digital GaAs logic processes of the 10-GHz GaAs family.

GaAs Logic Processes

Basic FET Process

MESFET

MESFET

Pseudomorphic-inverted HEMT

Pseudomorphic BP--MESFET

Basic Gate

Circuit

DCFL or SBFL

DCFL or SBFL

DCFL or SBFL

Analog

Photo Masking

I-line printing

PEL

PEL

Deep UV

Gate Length

(µm)

0.5

< 0.2

0.2

0.2

fT (GHz)

30

60

> 60

> 60

Gate Delays

(ps)

25

9

7

–

Application

< 2.4 Gbps standard cell

>12-Gbps hand-routed logic

> 20-Gbps low-density logic

Analog amplifier

The key to operating reliably at 10 Gbps is logic circuitry that can easily manipulate data at over 13 Gbps.

The higher frequency overhead is required to meet the different clock skews encountered when design-

ing and routing 10-Gbps data management hardware.

The logic is either direct-coupled FET logic (DCFL) or source-coupled FET logic (SCFL). The low-drive

disadvantage of DCFL can be improved by using super-buffer FET logic (SBFL). The basic speed of SBFL

is slower than DCFL, but SBFL is faster with higher fanouts and longer metal runs. A designer selects the

best performing logic for each logic element application. SBFLs used for clock distribution, output buff-

ers, etc. Typical gate delays of 9 ps and power of 2 mW per gate are achieved. Register logic elements like

D-flip flops are assembled using memory cell flip flops (MCFF) as shown in Figure 1.The operation speed

of a MCFF, which is about twice that of a conventional 6 NOR-gate circuit, operates at very low power.

To simplify device interconnections, AC-coupled clock and data input lines are created using the circuit

shown in Figure 2.

FEATURES

• 10-Gbps operation: highest speed available

• ECL level logic swings: easy interface to other

logic

• Inputs internally terminated: reduces noise and

phase jitter

• 50-Ω I/Os: easy to interconnect hardware

Oki Semiconductor

1

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