ASM1232LP 查看數據表（PDF） - PulseCore Semiconductor

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ASM1232LP

5V µP Power Supply Monitor and Reset Circuit

PulseCore Semiconductor 

November 2006

rev 1.6

Parameter

Input Leakage

RESET Low Level

Internal Pull-up Resistor

Operating Current (CMOS)

Input Capacitance

Output Capacitance

PBRST Manual Reset

Minimum Low Time

Reset Active Time

ST Pulse Width

VCC Fail Detect to RESET or

RESET

VCC Slew Rate

PBRST Stable LOW to RESET and

RESET Active

VCC Detect to RESET or RESET

inactive

VCC Slew Rate

Symbol

Conditions

IIL

VOL

ICC1

CIN

COUT

Note 1

Note 3

Note 1

tPB

PBRST = VIL

tRST

tST

Note 4

tRPD

tF

4.75V to 4.25V

tPDLY

tRPU

tR

tRISE = 5µs

4.25V to 4.75V

ASM1232LP/LPS

Min

Typ

Max

Unit

-1.0

1.0

µA

0.4

V

40

kΩ

30

µA

5

pF

10

pF

20

ms

250

610

1000

ms

20

ns

5

8

µs

300

µs

20

ms

250

610

1000

ms

0

ns

Notes

1. PBRST is internally pulled HIGH to VCC through a nominal 40kΩ resistor.

2. RESET is an open drain output.

3. RESET remains within 0.5V of VCC on power-down until VCC falls below 2V. RESET remains within 0.5V of ground on power-down until VCC

falls below 2.0V.

4. Must not exceed the minimum watchdog time-out period (tTD). The watchdogcircuit cannot be disabled. To avoid a reset, ST must be strobed.

5V µP Power Supply Monitor and Reset Circuit

Notice: The information in this document is subject to change without notice

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