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ATT3042

Field-Programmable Gate Arrays

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Data Sheet

February 1997

ATT3000 Series Field-Programmable Gate Arrays

Configuration (continued)

The specific data format for each device is produced by

the bit stream generation program, and one or more of

these files can then be combined and appended to a

length count preamble and be transformed into a

PROM format file by the PROM generation program of

the ORCA Foundry Development System. The tie

option of the bit stream generation program defines

output levels of unused blocks of a design and con-

nects these to unused routing resources. This prevents

indeterminate levels which might produce parasitic

supply currents. This tie option can be omitted for quick

breadboard iterations where a few additional mA of ICC

are acceptable.

The configuration bit stream begins with high preamble

bits, a 4-bit preamble code, and a 24-bit length count.

When configuration is initiated, a counter in the FPGA

is set to 0 and begins to count the total number of con-

figuration clock cycles applied to the device. As each

configuration data frame is supplied to the FPGA, it is

internally assembled into a data word. As each data

word is completely assembled, it is loaded in parallel

into one word of the internal configuration memory

array. The configuration loading process is complete

when the current length count equals the loaded length

count and the required configuration program data

frames have been written. Internal user flip-flops are

held reset during configuration.

Two user-programmable pins are defined in the uncon-

figured FPGA: high during configuration (HDC) and low

during configuration (LDC), and DONE/PROG may be

used as external control signals during configuration. In

master mode configurations, it is convenient to use LDC

as an active-low EPROM chip enable. After the last

configuration data bit is loaded and the length count

compares, the user I/O pins become active. Options in

the bit stream generation program allow timing choices

of one clock earlier or later for the timing of the end of

the internal logic reset and the assertion of the DONE

signal. The open-drain DONE/PROG output can be

AND-tied with multiple FPGAs and used as an active-

high READY, an active-low PROM enable, or a RESET

to other portions of the system. The state diagram of

Figure 18 illustrates the configuration process.

Lucent Technologies Inc.

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