ATT3042 查看數據表（PDF） - Unspecified

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ATT3042

Field-Programmable Gate Arrays

Unspecified 

Data Sheet

February 1997

ATT3000 Series Field-Programmable Gate Arrays

Configuration Modes (continued)

Slave Mode

Slave mode provides a simple interface for loading the FPGA configuration as shown in Figure 24. Serial data is

supplied in conjunction with a synchronizing input clock. Most slave mode applications are in daisy-chain configu-

rations in which the data input is supplied by the previous FPGA’s data out, while the clock is supplied by a lead

device in master or peripheral mode. Data may also be supplied by a processor or other special circuits.

SYSTEM

RESET

MICROCOMPUTER

I/O PORT

RESET

STRB

D0

D1

D2

D3

D4

D5

D6

D7

+5 V

M0 M1 PWRDWN

+5 V

CCLK

DIN

FPGA

M2

DOUT

HDC

LDC

D/P

INIT

RESET

OTHER

I/O PINS

5 kΩ

*

*

GENERAL-

PURPOSE

USER I/O

Figure 24. Slave Mode

5-3115(F)

Lucent Technologies Inc.

25

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