IDT74FCT16952ATEB 查看數據表（PDF） - Integrated Device Technology
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IDT74FCT16952ATEB Datasheet PDF : 8 Pages
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IDT73720 /A16-BIT TRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Signal
X(0:15)
Y(0:15)
Z(0:15)
LEXY
LEXZ
LEYX
LEZX
PATH
T/R
OEU
OEL
I/O
Description
I/O Bidirectional Data Port X. Usually connected to the CPU's A/D (Address/Data) bus.
I/O Bidirectional Data port Y. Connected to the even path or even bank of memory.
I/O Bidirectional Data port Z. Connected to the odd path or odd bank of memory.
I Latch Enable input for Y-Write Latch. The Y-Write Latch is open when LEXY is HIGH. Data from the X-port
(CPU) is latched on the HIGH-to-LOW transition of LEXY
I Latch Enable input for Z-Write Latch. The Z-Write Latch is open when LEXZ is HIGH. Data from the X-port
(CPU) is latched on the HIGH-to-LOW transition of LEXZ.
I Latch Enable input for the Y-Read Latch. The Y-Read Latch is open when LEYX is HIGH. Data from the even
path Y is latched on the HIGH-to-LOW transition of LEYX.
I Latch Enable input for the Z-Read Latch. The Z-Read Latch is open when LEZX is HIGH. Data from the odd
path Z is latched on the HIGH-to-LOW transition of LEZX
I Even/Odd Path Selection. When high, PATH enables data transfer between the X-Port and the Y-port (even
path). When LOW, PATH enables data transfer between the X-Port and the Z-Port (odd path).
I Transmit/Receive Data. When high, Port X is an input Port and either Port Y or Z is an output Port. When LOW,
Port X is an output Port while Ports Y & Z are input Ports
I Output Enable for Upper byte. When LOW, the Upper byte of data is transfered to the port specified by PATH in
the direction specified by T/R .
I Output Enable for Lower byte. When LOW, the Lower byte of data is transfered to the port specified by PATH in
the direction specified by T/R .
2527 tbl 02
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Com’l.
Mil.
Unit
VTERM
TA
TBIAS
Terminal Voltage
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
–0.5 to +7.0
0 to +70
–55 to +125
–0.5 to +7.0 V
–55 to +125 °C
–65 to +135 °C
TSTG
PT
Storage
Temperature
Power
Dissipation
–55 to +125 –65 to +125 °C
1.0
1.0
W
IOUT
DC Output
Current
50
50
mA
NOTE:
2527 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25°C, F = 1.0MHZ)
Symbol
CIN
COUT
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
VIN = 0V
VOUT = 0V
Max. Unit
8 pF
12 pF
NOTE:
2527 tbl 04
1. This parameter is guaranteed by device characterization, but is not prod-
uction tested.
TRUTH TABLE
Path
L
L
H
H
T/R OEU OEL Functionality
L
L
L
Z→X (16-bits)–Read Z(1)
H
L
L
X→Z (16 bits)–Write Z(1)
L
L
L
Y→X (16-bits)–Read Y(2)
H
L
L
X→Y (16 bits)–Write Y(2)
X
X
H
H All output buffers are
disabled
X
X
H
L Transfer of lower 8 bits
(0:7) as per PATH & T/R
X
X
L
H Transfer of upper 8 bits
(8:15) as per PATH & T/R
NOTES:
2527 tbl 01
1. For Z→X and X→Z transfers, Y-port output buffers are tristated.
2. For Y→X and X→Y transfers, Z-port output buffers are tristated.
11.5
3
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