PI74FCT162511TV 查看數據表（PDF） - Pericom Semiconductor
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PI74FCT162511TV Datasheet PDF : 8 Pages
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PI74FCT16511/162511T
16-BIT REGISTERED/
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Product Pin Description
Product Pin Configuration
Pin Name
OEAB
OEBA
CLKAB
CLKBA
LEAB
LEBA
PERA
PERB
Ax
Bx
ODD/EVEN(1)
GEN/CHK(1)
PAx(2)
PBx
GND
VCC
Description
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Clock Input
B-to-A Clock Input
A-to-B Latch Enable Input
B-to-A Latch Enable Input
Parity Error (Open Drain) on A Outputs
Parity Error (Open Drain) on B Outputs
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or B-to-A 3-State Outputs
Parity Mode Selection Input
A-to-B Port Generate or Check Mode Input
A-to-B Parity Input, B-to-A Parity Output
B-to-A Parity Input, A-to-B Parity Output
Ground
Power
NOTES:
1. ODD/EVEN and GEN/CHK should be tied to VCC or GND with no resistor
for optimum results.
2. The PAx pin input is internally disabled during parity generation. This means
that when generating parity in the A-to-B direction, there is no need to add a
pull-up resistor to guarantee state. The pin will still function properly as the
parity output for the B-to-A direction.
OEAB 1
56
LEAB 2
55
PA1 3
54
GND 4
53
A0 5
52
A1 6
51
VCC 7
50
A2 8
49
A3 9
48
A4 10
47
A5 11
46
A6 12 56-PIN 45
A7 13 V56 44
GND 14 A56 43
PERA 15
42
A8 16
41
A9 17
40
A10 18
39
A11 19
38
A12 20
37
A13 21
36
VCC 22
35
A14 23
34
A15 24
33
GND 25
32
PA2 26
31
OEBA 27
30
LEBA 28
29
GENCHK
CLKAB
PB1
GND
B0
B1
VCC
B2
B3
B4
B5
B6
B7
PERB
GND
B8
B9
B10
B11
B12
B13
VCC
B14
B15
GND
PB2
CLKBA
ODD/EVEN
Capacitance (TA = 25°C, f = 1 MHz)
Parameters(1)
Description
Test Conditions
Typ
CIN
Input Capacitance
VIN = 0V
4.5
CI/O
I/O Capacitance
VOUT = 0V
5.5
CO
Open Drain Capacitance
VOUT = 0V
4.5
Note:
1. This parameter is determined by device characterization but is not production tested.
Max.
6.0
8.0
6.0
Units
pF
pF
pF
3
PS2080A 01/15/95
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