CAT28C64BXI90 查看數據表（PDF） - ON Semiconductor

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CAT28C64BXI90

64K-Bit CMOS PARALLEL EEPROM

ON Semiconductor 

CAT28C64B

DEVICE OPERATION

Read

Data stored in the CAT28C64B is transferred to the data

bus when WE is held high, and both OE and CE are held

low. The data bus is set to a high impedance state when

either CE or OE goes high. This 2-line control architec-

ture can be used to eliminate bus contention in a system

environment.

Byte Write

A write cycle is executed when both CE and WE are low,

and OE is high. Write cycles can be initiated using either

WE or CE, with the address input being latched on the

falling edge of WE or CE, whichever occurs last. Data,

conversely, is latched on the rising edge of WE or CE,

whichever occurs first. Once initiated, a byte write cycle

automatically erases the addressed byte and the new

data is written within 5 ms.

Figure 3. Read Cycle

ADDRESS

CE

OE

WE

DATA OUT

tRC

tCE

tOE

VIH

tLZ

HIGH-Z

tOLZ

tOH

DATA VALID

tAA

tOHZ

tHZ

DATA VALID

Figure 4. Byte Write Cycle [WE Controlled]

ADDRESS

CE

tAS

tAH

tCS

tWC

tCH

OE

tOES

WE

DATA OUT

DATA IN

© 2009 SCILLC. All rights reserved.

Characteristics subject to change without notice

tWP

HIGH-Z

tOEH

tBLC

DATA VALID

7

Doc. No. MD-1011, Rev. I

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