AD7865-1(1999) 查看數據表（PDF） - Analog Devices

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AD7865-1
(Rev.:1999)

Four-Channel, Simultaneous Sampling, Fast, 14-Bit ADC

Analog Devices 

AD7865-3

Figure 4 shows the analog input section of the AD7865-3. The

analog input range is ± 2.5 V on the VINxA input. The VINxB

input can be left unconnected but if it is connected to a poten-

tial then that potential must be AGND.

6k⍀

VREF

R2

VINxA

VINxB

+2.5V

REFERENCE

AD7865-3

TO ADC

REFERENCE

CIRCUITRY

R1

TRACK/

HOLD

TO INTERNAL

COMPARATOR

Figure 4. AD7865-3 Analog Input Structure

For the AD7865-3, R1 = 4 kΩ and R2 = 4 kΩ. As a result, the

VINxA input should be driven from a low impedance source. The

resistor input stage is followed by the high input impedance

stage of the track/hold amplifier.

The designed code transitions take place midway between suc-

cessive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs

etc.) LSB size is given by the formula, 1 LSB = FSR/16384.

Output coding is twos complement binary with 1 LSB = FSR/

16384 = 5 V/16384 = 610.4 µV. The ideal input/output transfer

function for the AD7865-3 is shown in Table III.

Table III. Ideal Input/Output Code Table for the AD7865-3

Analog Input1

+FSR/2 – 3/2 LSB2

+FSR/2 – 5/2 LSB

+FSR/2 – 7/2 LSB

Digital Output Code Transition

011 . . . 110 to 011 . . . 111

011 . . . 101 to 011 . . . 110

011 . . . 100 to 011 . . . 101

AGND + 3/2 LSB

AGND + 1/2 LSB

AGND – 1/2 LSB

AGND – 3/2 LSB

000 . . . 001 to 000 . . . 010

000 . . . 000 to 000 . . . 001

111 . . . 111 to 000 . . . 000

111 . . . 110 to 111 . . . 111

–FSR/2 + 5/2 LSB

–FSR/2 + 3/2 LSB

–FSR/2 + 1/2 LSB

100 . . . 010 to 100 . . . 011

100 . . . 001 to 100 . . . 010

100 . . . 000 to 100 . . . 001

NOTES

1FSR is full-scale range is 5 V, with VREF = +2.5 V.

21 LSB = FSR/16384 = 610.4 µV (± 2.5 V—AD7865-3) with VREF = +2.5 V.

SELECTING A CONVERSION SEQUENCE

Any subset of the four channels VIN1 to VIN4 can be selected for

conversion. The selected channels are converted in an ascending

order. For example if the channel selection includes VIN4, VIN1

and VIN3 then the conversion sequence will be VIN1, VIN3 and

then VIN4. The conversion sequence selection may be made by

using either the hardware channel select input pins SL1 through

SL4 (if H/S is tied low) or programming the channel select

register (if H/S is tied high). A logic high on a hardware channel

select pin (or logic one in the channel select register) when

CONVST goes logic high, marks the associated analog input

channel for inclusion in the conversion sequence.

AD7865

Figure 5 shows the arrangement used. The H/S SEL controls a

multiplexer that selects the source of the conversion sequence

information, i.e., from the hardware channel select pins (SL1 to

SL4) or from the channel selection register. When a conversion

is started the output from the multiplexer is latched until the

end-of-the conversion sequence. The data bus bits DB0 to DB3

(DB0 representing Channel 1 through DB3 representing Chan-

nel 4) are bidirectional and become inputs to the channel select

register when RD is logic high and CS and WR are logic low.

The logic state on DB0 to DB3 is latched into the channel select

register when WR goes logic high. Figure 6 shows the loading

sequence for channel selection using software control. When

using software control to select the conversion sequence a write

is only required each time the conversion sequence needs chang-

ing. This is because the channel select register will hold its in-

formation until different information is written to it.

It should be noted that the hardware select Pins SL1 and SL2

are dual function. When H/S SEL is logic low (selecting the

conversion sequence using software control) they take the func-

tions CLK IN and INT/EXT CLK respectively. Therefore, the

logic inputs on these pins must be set according to the type of

operation required (see Using an External Clock). Also when

H/S SEL is high, the SL3 and SL4 logic inputs have no function

and can be tied either high or low, but should not be left floating.

H/S

HARDWARE CHANNEL

SELECT PINS

SL1

SL2

DATA BUS

SL3

D3 D2 D1 D0

SL4

SELECT INDIVIDUAL

TRACK-AND-HOLDS

FOR CONVERSION

CHANNEL

SELECT

REGISTER

MULTIPLEXER

LATCH

SEQUENCER

WR

CS

TRANSPARENT WHILE WAITING FOR CONVST.

WR

LATCHED ON THE RISING EDGE OF CONVST AND

DURING A CONVERSION SEQUENCE.

Figure 5. Channel Select Inputs and Registers

RD

WR

CS

DATA

t 13

t 14

t 15

t 16

t 17

DATA IN

Figure 6. Channel Selection via Software Control

REV. A

–11–

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