AD7865 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
生产厂家
AD7865 Datasheet PDF : 19 Pages
| |||
AD7865
TIMING CHARACTERISTICS1, 2 (VDD = 5 V ؎ 5%, AGND = DGND = 0 V, VREF = Internal, Clock = Internal; all specifications
TMIN to TMAX unless otherwise noted.)
Parameter
A, B, Y Versions Unit
Test Conditions/Comments
tCONV
tACQ
tBUSY
tWAKE-UP—External VREF3
t1
t2
Read Operation
t3
t4
t5
t64
t75
t8
t9
t10
t11
t12
Write Operation
t13
t14
t15
t16
t17
External Clock
t18
2.4
3.2
0.35
No. of Channels
× (tCONV)
1
35
70
0
0
35
35
40
5
30
15
120
180
70
15
0
20
0
0
5
5
200
µs max
µs max
µs max
µs max
µs max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Conversion Time, Internal Clock
Conversion Time, External Clock (5 MHz)
Acquisition Time
Selected Number of Channels Multiplied by tCONV
STBY Rising Edge to CONVST Rising Edge
CONVST Pulsewidth
CONVST Rising Edge to BUSY Rising Edge
CS to RD Setup Time
CS to RD Hold Time
Read Pulsewidth
Data Access Time after Falling Edge of RD, VDRIVE = 5 V
Data Access Time after Falling Edge of RD, VDRIVE = 3 V
Bus Relinquish Time after Rising Edge of RD
Time Between Consecutive Reads
EOC Pulsewidth
RD Rising Edge to FRSTDATA Edge (Rising or Falling)
EOC Falling Edge to FRSTDATA Falling Delay
EOC to RD Delay
WR Pulsewidth
CS to WR Setup Time
WR to CS Hold Time
Input Data Setup Time of Rising Edge of WR
Input Data Hold Time
CONVST Falling Edge to CLK Rising Edge
NOTES
1Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 6, 7 and 8.
3Refer to the Standby Mode Operation section. The MAX specification of 1 µs is valid when using a 0.1 µF decoupling capacitor on the VREF pin.
4Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
5These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
1.6mA
TO OUTPUT
PIN
50pF
1.6V
400A
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
–4–
REV. B
Share Link: 