CXB1582Q 查看數據表（PDF） - Sony Semiconductor

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CXB1582Q

Fibre Channel Receiver

Sony Semiconductor 

CXB1582Q

Pin

No.

Symbol

Type

Typical pin

I/O voltage

VCCE

Equivalent circuit

VCCG

Description

43 SDIN∗

44 SDIN

ECL

input

(differen

-tial)

ECL level

SDIN

SDIN∗

VEEE

45,

58

VCCE

Power

supply

3.3V

—

VCCE

46 LBIN∗

47 LBIN

ECL

input

(differen

-tial)

ECL level

LBIN

LBIN∗

VEEE

VCCE

48 EXCLK

ECL

input

ECL level

EXCLK

VEEE

49 VCCP

Power

supply

3.3V

—

External

part

50 REXT

connec

—

-tion

pin

51 VEEP1

Power

supply

0V

52 VEEP2

Power

supply

0V

—

—

–7–

VCCE – 1.3V

Serial data inputs.

These input pins are

enabled when SHD

is set to low level.

VEEG

VCCG

Positive power

supplies for ECL I/O.

VCCE – 1.3V

Serial data inputs for

loop-back test.

These input pins are

enabled when LBEN

is set to high level.

VEEG

VCCG

VCCE – 1.3V

VEEG

External clock input.

When ECLKSEL∗ is

set to low level, the

clock input to this pin

is used as the bit rate

clock. This pin is

biased to become

low level when left

open.

VCCP

REXT

VEEP2

Positive power supply

for internal PLL.

Connects the

resistor which

determines the VCO

center frequency.

Connect a 4.7kΩ

resistor between this

pin and VEEP1. (See

Notes on Operation

and Fig. 1.)

Negative power

supply for internal

PLL.

Negative power

supply for internal

PLL.

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