DLG4137 查看數據表（PDF） - OSRAM GmbH
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DLG4137 Datasheet PDF : 4 Pages
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Table 2. Pin description
VCC
Positive Supply +5 volts
GND
Ground
D0-D6
Data Lines, see Figure 3 (Character set)
CE
Chip Enable (active low)
This determines which device in an array will
accept data
WR
Write (active low) Data and chip enable must be
present and stable before and after the write
pulse (see data sheet for timing)
BL0, BL1 Blanking Control Input (active low)
Used to control the level of display brightness
LT
Lamp Test (active low)
Causes all dots to light at 1⁄2 brightness
Operation
In a dot matrix display system, it is advantageous to use a mul-
tiplexed approach with 12 drivers (5 digit plus 7 segments)
rather than 35 segment drivers. This obviously reduces the
number of drivers and interconnections required. A multiplexed
system must be a synchronous system, or the digits or ele-
ments may have different on (lit) times and therefore varying
brightness.
The DLO4135/DLG4137 is an internally multiplexed display, but
the data entry is asynchronous. Loading data is similar to writ-
ing into a RAM. Present the data, select the chip, and give a
write signal. For a multi digit system, each digit has its own
unique address location and will display its contents until
replaced by another code. The waveforms of Figure 4 shows
the relationship of the signals required to generate a write
cycle. Check the data sheet for minimum values required for
each signal.
Figure 3. Character set
D0 0
10
1
0
1
0
1
0
10
1
0
1
0
1
ASCII D1 0
01
1
0
0
1
1
0
01
1
0
0
1
1
CODE D2 0
00
0
1
1
1
1
0
00
0
1
1
1
1
D3 0
00
0
0
0
0
0
1
11
1
1
1
1
1
D6 D5 D4 HEX 0
12
3
4
5
6
7
8
9A
BCDE
F
000 0
Figure 4. Timing characteristics
WR
TW
TCES
CE
TDH
D0 – D6
TDS
Display Blanking and Dimming
The DLO4135/DLG4137 Intelligent Display has the capability of
three levels of brightness plus blank. Figure 5 shows the com-
bination of BL0 and BL1 for the different levels of brightness.
The BL0 and BL1 inputs are independent of write and chip
enable and does not affect the contents of the internal mem-
ory. A flashing display can be achieved by pulsing the blanking
pins at a 1–2 hertz rate. Either BL0 or BL1 should be held high
to light up the display.
Table 3. Dimming and blanking control
Brightness Level
BL1
BL0
Blank
0
0
1/ 7 brightness
0
1
1/ 2 brightness
1
0
full brightness
1
1
Lamp Test
The lamp test when activated causes all dots on the display to
be illuminated at 1/7 brightness. It does not destroy any previ-
ously stored characters. The lamp test function is independent
of chip enable, write, and the settings of the blanking inputs.
This convenient test gives a visual indication that all dots are
functioning properly. The lamp test can be used as a cursor or
pointer in a line of displays because it does not affect the dis-
play memory.
001 1
010 2
011 3
100 4
101 5
110 6
111 7
1. High=1 level. 2. Low=0 level.
General Design Considerations
When using the DLO4135/DLG4137 on a separate display
board having more than 6 inches of cable length, it may be nec-
essary to buffer all of the input lines. A non-inverting 74LS244
buffer can be used. The object is to prevent current transient
into the DLO4135/DLG4137 protection diodes. The buffers
should be located on the display board and as close to the dis-
plays as possible.
Because of high switching currents caused by the multiplex-
ing, local power supply by-pass-capacitors are also needed in
many cases. These should be 10 voIt, tantalum type having
10 uf capacitance. The capacitors may only be required every
2 displays depending on the line regulation and other noise
generators.
Decoupling capacitors should also be used across VCC and
ground of each display. Typical value of these capacitors is
0.01 mF/ 10 V.
2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA
www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
2
Appnote 28
May 31, 2000-13
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