DS28E01-100 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS28E01-100

1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine

Dallas Semiconductor -> Maxim Integrated 

Abridged Data Sheet

DS28E01-100

PARAMETER

EEPROM

Programming Current

Programming Time

Write/Erase Cycles (En-

durance) (Notes 21, 22)

Data Retention

(Notes 23, 24, 25)

SHA-1 ENGINE

SHA Computation Current

(Notes 5, 19)

SHA Computation Time

(Note 5)

SYMBOL

CONDITIONS

IPROG

tPROG

NCY

tDR

(Notes 5, 19)

(Note 20)

At 25°C

At 85°C (worst case)

At 85°C (worst case)

ILCSHA

tCSHA

See full version of data sheet.

See full version of data sheet.

MIN

TYP

MAX UNITS

200k

50k

40

0.8

mA

10

ms

---

years

mA

ms

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Specifications at TA = -40°C are guaranteed by design only and not production-tested.

System requirement.

Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The

specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily

loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.

Maximum value represents the internal parasite capacitance when VPUP is first applied. If RPUP = 2.2kΩ, 2.5µs after VPUP has been

applied the parasite capacitance will not affect normal communications.

Guaranteed by design, characterization and/or simulation only. Not production tested.

VTL, VTH, and VHY are a function of the internal supply voltage, which is itself a function of VPUP, RPUP, 1-Wire timing, and capacitive

loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY.

Voltage below which, during a falling edge on IO, a logic 0 is detected.

The voltage on IO needs to be less than or equal to VIL(MAX) at all times the master is driving IO to a logic-0 level.

Voltage above which, during a rising edge on IO, a logic 1 is detected.

After VTH is crossed during a rising edge on IO, the voltage on IO has to drop by at least VHY to be detected as logic '0'.

The I-V characteristic is linear for voltages less than 1V.

Applies to a single device attached to a 1-Wire line.

The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising edge.

Defines maximum possible bit rate. Equal to tW0L(min) + tREC(min).

Interval after tRSTL during which a bus master is guaranteed to sample a logic-0 on IO if there is a DS28E01-100 present.

Minimum limit is tPDH(max); maximum limit is tPDH(min) + tPDL(min).

Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table below.

ε in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual maximum

duration for the master to pull the line low is tW1Lmax + tF - ε and tW0Lmax + tF - ε respectively.

δ in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input high threshold

of the bus master. The actual maximum duration for the master to pull the line low is tRLmax + tF.

Current drawn from IO during EEPROM programming or SHA-1 computation interval.

See full version of data sheet.

Write-cycle endurance is degraded as TA increases.

Not 100% production-tested; guaranteed by reliability monitor sampling.

Data retention is degraded as TA increases.

Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet

limit at operating temperature range is established by reliability testing.

EEPROM writes may become non-functional after the data retention time is exceeded. Long-time storage at elevated

temperatures is not recommended; the device may lose its write-capability after 10 years at 125°C or 40 years at 85°C.

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