EN5360DC 查看數據表（PDF） - Unspecified
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EN5360DC Datasheet PDF : 11 Pages
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Rev 1.0 – July 2005
EN5360
It is recommended that Rb1 and Rb2 resistor values
be ~2kΩ. Use the following equation to set the
resistor Ra1 for the desired output voltage:
Ra1 = (Vout − 0.8V ) * Rb1
0.8V
If over-voltage protection is desired, use the following
equation to set the resistor Ra2 for the desired OVP
trip-point:
Ra2 = (OVPtrip − 0.96V ) * Rb2
0.96V
By design, if both resistor dividers are the same, the
OV trip-point will be 20% above the nominal output
voltage.
Figure 1: External output voltage and OVP setting
22µF
PVIN VOUT
AVIN
Ra2
PGND
XOV
XFB
SS
VOUT
Ra1
Rb2
Rb1
15 nF
47µF
PGND
AGND
AGND
Table 1: Output Voltage Select Table
VS2* VS1* VS0* Output Voltage
0
0
0
3.3V
0
0
1
2.5V
0
1
0
1.8V
0
1
1
1.5V
1
0
0
1.25V
1
0
1
1.2V
1
1
0
0.8V**
1
1
1 User Selectable
** 0.8V ref only, not guaranteed performance
* The VS0, VS1 and VS2 pins are defaulted to a ‘1’
with an internal pull-up resistor. Only connect
these pins to AGND if a ‘0’ is required. If a ‘1’ is
required, then leave the pin floating.
Capacitor Selection
The EN5360 needs about 40-80uF of input
capacitance. Low-cost, low-ESR ceramic capacitors
can be used as input capacitors for this converter and
it is strongly recommended that they be rated X5R or
X7R. In some applications, lower value capacitors are
needed in parallel with the larger, lossy capacitors in
order to provide high frequency decoupling.
The EN5360 has been optimized for use with about
50µF of ceramic output capacitance. It is strongly
recommended that these be low-cost, low-ESR,
ceramic capacitors rated X5R or X7R. (See the
Enpirion application note on ripple comparison for
optimum selection of number and value of these
capacitors based on ripple requirements.) In order to
eliminate high-frequency switching spikes on the
output ripple, usually a low-value, low-ESR ceramic
capacitor is used in parallel with the larger capacitors
right at the load.
Enable Operation
The ENABLE pin provides a means to shut down the
power FET switching or enable normal operation. A
logic low will disable the converter and cause it to
shut down. A logic high will enable the converter into
normal operation.
Soft-Start Operation
The SS pin in conjunction with a small capacitor
between this pin and AGND provides the soft start
function to limit the in-rush current during start-up.
During start-up of the converter the reference voltage
to the error amplifier is gradually increased to its final
level by an internal current source of typically 10uA.
The whole soft-start procedure is designed to take 1ms
- 3ms with a 15-30nF soft start capacitor, but can be
programmed by capacitor selection using the
following equation:
Rise Time: TR = Css* 80k
During the soft-start cycle, when the soft-start
capacitor reaches 0.8V, the output has reached its
programmed regulation range. Note that the soft-start
current source will continue to operate and during
normal operation, the soft-start capacitor will charge
up to a final value of 2.5V.
8
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