SST89E554 查看數據表（PDF） - Silicon Storage Technology

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SST89E554

Flash flex 51 MCU

Silicon Storage Technology 

Auxiliary Register (AUXR)

Location

7

6

8EH

-

-

FlashFlex51 MCU

SST89E564 / SST89V564 / SST89E554 / SST89V554

Preliminary Specifications

5

4

3

2

1

0

Reset Value

-

-

-

-

EXTRAM

AO

xxxxxx00b

Symbol

EXTRAM

AO

Function

0: Internal Expanded RAM access. For details, refer to “Data Memory” on page 12.

1: External data memory access.

0: Normal ALE

1: ALE is normally off. ALE is active only during a MOVX or MOVC instruction. This will reduce

EMI.

Auxiliary Register 1 (AUXR1)

Location

7

6

5

A2H

-

-

-

4

3

2

-

GF2

0

1

0

Reset Value

-

DPS

xxxx00x0b

Symbol

GF2

DPS

Function

General purpose user-defined flag.

DPTR registers select bit.

0: DPTR0 is selected.

1: DPTR1 is selected.

Watchdog Timer Control Register (WDTC)

Location

7

6

5

4

0C0H

-

-

-

WDOUT

3

WDRE

2

WDTS

1

WDT

0

Reset Value

SWDT xxx00x00b

Symbol

WDOUT

WDRE

WDTS

WDT

SWDT

Function

Watchdog output enable.

0: Watchdog reset will not be exported on Reset pin.

1: Watchdog reset if enabled by WDRE, will assert Reset pin for 32 clocks.

Watchdog timer reset enable.

0: Disable watchdog timer reset.

1: Enable watchdog timer reset.

Watchdog timer reset flag.

0: External hardware reset clears the flag.

Flag can also be cleared by writing a 1.

Flag survives if chip reset happened because of watchdog timer overflow.

1: Hardware sets the flag on watchdog overflow.

Watchdog timer refresh.

0: Hardware resets the bit when refresh is done.

1: Software sets the bit to force a watchdog timer refresh.

Start watchdog timer.

0: Stop WDT.

1: Start WDT.

©2001 Silicon Storage Technology, Inc.

20

S71181-03-000 9/01 384

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