PSD834F2-10J 查看數據表（PDF） - STMicroelectronics

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PSD834F2-10J

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

PSD834F2V

KEY FEATURES

■ A simple interface to 8-bit microcontrollers that

use either multiplexed or non-multiplexed

busses. The bus interface logic uses the control

signals generated by the microcontroller

automatically when the address is decoded and

a READ or WRITE is performed. A partial list of

the MCU families supported include:

■ 27 individually configurable I/O port pins that

can be used for the following functions:

– MCU I/Os

– PLD I/Os

– Latched MCU address output

– Special function I/Os.

– Intel 8031, 80196, 80186, 80C251, and

80386EX

– 16 of the I/O ports may be configured as

open-drain outputs.

– Motorola 68HC11, 68HC16, 68HC12, and

■ Standby current as low as 25µA.

683XX

■ Built-in JTAG compliant serial port allows full-

– Philips 8031 and 8051XA

chip In-System Programmability (ISP). With it,

– Zilog Z80 and Z8

you can program a blank device or reprogram a

■ Internal 2 Mbit Flash memory. This is the main

device in the factory or the field.

Flash memory. It is divided into 8 equal-sized

■ Internal page register that can be used to

blocks that can be accessed with user-specified

expand the microcontroller address space by a

addresses.

■ Internal secondary 256 Kbit Flash boot memory.

t(s) It is divided into 4 equal-sized blocks that can be

accessed with user-specified addresses. This

c secondary memory brings the ability to execute

u code and update the main Flash concurrently.

d ■ Internal 64 Kbit SRAM.

ro ■ CPLD with 16 Output macrocells (OMCs) and

P 24 Input macrocells (IMCs). The CPLD may be

te used to efficiently implement a variety of logic

functions for internal and external control.

le Examples include state machines, loadable

o shift registers, and loadable counters.

bs ■ Decode PLD (DPLD) that decodes address for

Obsolete Product(s) - O selection of internal memory blocks.

factor of 256.

■ Internal programmable Power Management

Unit (PMU) that supports a low power mode

called Power Down Mode. The PMU can

automatically detect a lack of microcontroller

activity and put the PSD into Power-down

mode.

■ Erase/WRITE cycles:

– Flash memory – 100,000 minimum

– PLD – 1,000 minimum

– Data Retention: 15 year minimum (for Main

Flash memory, Boot, PLD and Configuration

bits)

6/95

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