PSD834F2-10J 查看數據表（PDF） - STMicroelectronics
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PSD834F2-10J
STMicroelectronics
PSD834F2-10J Datasheet PDF : 95 Pages
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PSD834F2V
PSD ARCHITECTURAL OVERVIEW
PSD devices contain several major functional
blocks. Figure 2 shows the architecture of the PSD
device family. The functions of each block are de-
scribed briefly in the following sections. Many of
the blocks perform multiple functions and are user
configurable.
Memory
Table 1. PLD I/O
Name
Inputs
Outputs
Product
Terms
Decode PLD (DPLD) 73
17
42
Complex PLD (CPLD) 73
19
140
Each of the memory blocks is briefly discussed in
the following paragraphs. A more detailed discus- The DPLD is used to decode addresses and to
sion can be found in the section entitled “MEMO- generate Sector Select signals for the PSD inter-
RY BLOCKS“ on page 15.
nal memory and registers. The DPLD has combi-
The 2 Mbit (256K x 8) Flash memory is the primary
memory of the PSD. It is divided into 8 equally-
sized sectors that are individually selectable.
natorial outputs. The CPLD has 16 Output
Macrocells (OMC) and 3 combinatorial outputs.
The PSD also has 24 Input Macrocells (IMC) that
can be configured as inputs to the PLDs. The
The 256 Kbit (32K x 8) secondary Flash memory PLDs receive their inputs from the PLD Input Bus
is divided into 4 equally-sized sectors. Each sector and are differentiated by their output destinations,
is individually selectable.
The 64 Kbit SRAM is intended for use as a
) scratch-pad memory or as an extension to the
t(s MCU SRAM.
c Each sector of memory can be located in a differ-
u ent address space as defined by the user. The ac-
d cess times for all memory types includes the
ro address latching and DPLD decoding time.
P Page Register
te The 8-bit Page Register expands the address
range of the MCU by up to 256 times. The paged
le address can be used as part of the address space
o to access external memory and peripherals, or in-
s ternal memory and I/O. The Page Register can
b also be used to change the address mapping of
O sectors of the Flash memories into different mem-
- ory spaces for IAP.
t(s) PLDs
The device contains two PLDs, the Decode PLD
c (DPLD) and the Complex PLD (CPLD), as shown
u in Table 1, each optimized for a different function.
d The functional partitioning of the PLDs reduces
ro power consumption, optimizes cost/performance,
Obsolete P and eases design entry.
number of product terms, and macrocells.
The PLDs consume minimal power. The speed
and power consumption of the PLD is controlled
by the Turbo Bit in PMMR0 and other bits in the
PMMR2. These registers are set by the MCU at
run-time. There is a slight penalty to PLD propaga-
tion time when invoking the power management
features.
I/O Ports
The PSD has 27 individually configurable I/O pins
distributed over the four ports (Port A, B, C, and
D). Each I/O pin can be individually configured for
different functions. Ports can be configured as
standard MCU I/O ports, PLD I/O, or latched ad-
dress outputs for MCUs using multiplexed ad-
dress/data buses.
The JTAG pins can be enabled on Port C for In-
System Programming (ISP).
Ports A and B can also be configured as a data
port for a non-multiplexed bus.
MCU Bus Interface
PSD interfaces easily with most 8-bit MCUs that
have either multiplexed or non-multiplexed ad-
dress/data buses. The device is configured to re-
spond to the MCU’s control signals, which are also
used as inputs to the PLDs. For examples, please
see the section entitled “MCU Bus Interface Exam-
ples“ on page 41.
8/95
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