PSD834F2-10J 查看數據表（PDF） - STMicroelectronics

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PSD834F2-10J

Flash PSD, 3.3V Supply, for 8-bit MCUs 2 Mbit + 256 Kbit Dual Flash Memories and 64 Kbit SRAM

STMicroelectronics 

PSD834F2V

JTAG Port

In-System Programming (ISP) can be performed (APD) Unit that turns off device functions during

through the JTAG signals on Port C. This serial in- MCU inactivity. The APD Unit has a Power-down

terface allows complete programming of the entire mode that helps reduce power consumption.

PSD device. A blank device can be completely

programmed. The JTAG signals (TMS, TCK,

TSTAT, TERR, TDI, TDO) can be multiplexed with

other functions on Port C. Table 2 indicates the

JTAG pin assignments.

The PSD also has some bits that are configured at

run-time by the MCU to reduce power consump-

tion of the CPLD. The Turbo Bit in PMMR0 can be

reset to '0' and the CPLD latches its outputs and

goes to sleep until the next transition on its inputs.

In-System Programming (ISP)

Additionally, bits in PMMR2 can be set by the

Using the JTAG signals on Port C, the entire PSD MCU to block signals from entering the CPLD to

device can be programmed or erased without the reduce power consumption. Please see the sec-

use of the MCU. The primary Flash memory can

tion entitled “POWER MANAGEMENT” on page

also be programmed in-system by the MCU

56 for more details.

executing the programming algorithms out of the

secondary memory, or SRAM. The secondary

memory can be programmed the same way by

Table 2. JTAG SIgnals on Port C

executing out of the primary Flash memory. The

Port C Pins

JTAG Signal

PLD or other PSD Configuration blocks can be

programmed through the JTAG port or a device

PC0

t(s) programmer. Table 3 indicates which

PC1

programming methods can program different

c functional blocks of the PSD.

PC3

u Power Management Unit (PMU)

PC4

rod The Power Management Unit (PMU) gives the

PC5

user control of the power consumption on selected

P functional blocks based on system requirements. PC6

te The PMU includes an Automatic Power-down

TMS

TCK

TSTAT

TERR

TDI

TDO

le Table 3. Methods of Programming Different Functional Blocks of the PSD

so Functional Block

JTAG Programming Device Programmer

IAP

b Primary Flash Memory

Yes

Yes

Yes

- O Secondary Flash Memory

Yes

Yes

Yes

t(s) PLD Array (DPLD and CPLD)

Yes

Yes

No

Obsolete Produc PSD Configuration

Yes

Yes

No

9/95

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