F25L016A 查看數據表（PDF） - [Elite Semiconductor Memory Technology Inc.
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F25L016A Datasheet PDF : 32 Pages
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ESMT
F25L016A
capacity.
11. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other.
The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both instructions
effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR can reset WREN.
Read (33 MHz)
The Read instruction supports up to 33 MHz, it outputs the data
starting from the specified address location. The data output
stream is continuous through all addresses until terminated by a
low to high transition on CE . The internal address pointer will
automatically increment until the highest memory address is
reached. Once the highest memory address is reached, the
address pointer will automatically increment to the beginning
(wrap-around) of the address space, i.e. for 16Mbit density, once
the data from address location 1FFFFFH had been read, the next
output will be from address location 00000H.
The Read instruction is initiated by executing an 8-bit command,
03H, followed by address bits [A23-A0]. CE must remain active
low for the duration of the Read cycle. See Figure 2 for the Read
sequence.
CE
MODE3 1 2 3 4 5 6 7 8
15 16
23 24
31 32 39 40 47 48 55 56
63 64
70
SCK MODE1
SI
03
ADD.
ADD.
ADD.
MSB
MSB
HIGH IMPENANCE
SO
N
DOU T
MSB
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
D OU T
Figure 2 : READ SEQUENCE
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2008
Revision: 1.4
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