HCTL-2001 查看數據表（PDF） - Avago Technologies

零件编号

产品描述 (功能)

生产厂家

HCTL-2001

Quadrature Decoder/Counter Interface ICs

Avago Technologies 

Figure 11. Typical Interface Timing

Actions

1. On the rising edge of the clock, counter data is

transferred to the position data latch, provided the

inhibit signal is low.

2. When OE goes low, the outputs of the multiplexer are

enabled onto the data lines. If SEL is low, then the

high order data bytes are enabled onto the data lines.

If SEL is high, then the low order data bytes are

enabled onto the data lines.

3. When the IC detects a low on OE and SEL during a

falling clock edge, the internal inhibit signal is

activated. This blocks new data from being transferred

from the counter to the position data latch.

4. When SEL goes high, the data outputs change from

the high byte to the low byte.

5. The first of two reset conditions for the inhibit logic is

met when the IC detects a logic high on SEL and a

logic low on OE during a falling clock edge.

6. When OE goes high, the data lines change to a high

impedance state.

7. The IC detects a logic high on OE during a falling clock

edge. This satisfies the second reset condition for the

inhibit logic.

11

Share Link: