DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

HD74LV4040AFPEL 查看數據表(PDF) - Renesas Electronics

零件编号
产品描述 (功能)
生产厂家
HD74LV4040AFPEL
Renesas
Renesas Electronics Renesas
HD74LV4040AFPEL Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
HD74LV4040A
Switching Characteristics
Item
Maximum
clock frequency
Propagation
delay time
Propagation
delay time skew
Setup time
Symbol
fmax
tPLH/tPHL
tPHL
tpd
Ta = 25°C
Min Typ
50 90
30 60
— 10.0
— 12.7
— 9.9
— 11.8
— 3.0
tSU
7.0 —
Max
16.0
19.6
15.4
18.0
5.5
Ta = –40 to 85°C
Min
Max
40
25
1.0
18.3
1.0
22.2
1.0
17.5
1.0
20.4
6.3
7.0
Test
Unit Conditions
MHz
ns
ns
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 50 pF
ns
Pulse width
tw
7.0 — — 7.0
ns
7.0 — — 7.0
Item
Maximum
clock frequency
Propagation
delay time
Propagation
delay time skew
Setup time
Symbol
fmax
tPLH/tPHL
tPHL
tpd
Ta = 25°C
Min Typ
75 140
55 80
— 7.5
— 10.0
— 8.3
— 10.8
— 2.4
tSU
5.0 —
Max
11.9
15.4
12.8
16.3
4.4
Ta = –40 to 85°C
Min
Max
70
50
1.0
14.0
1.0
17.5
1.0
15.0
1.0
18.5
5.0
5.0
Test
Unit Conditions
MHz
ns
ns
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 50 pF
ns
Pulse width
tw
5.0 — — 5.0
ns
5.0 — — 5.0
VCC = 2.5 ± 0.2 V
FROM TO
(Input) (Output)
CLK
Q1
CLR
Qn
Qn+1
CLR inactive before
CLK
CLK high or low
CLR high
VCC = 3.3 ± 0.3 V
FROM TO
(Input) (Output)
CLK
Q1
CLR
Qn
Qn+1
CLR inactive before
CLK
CLK high or low
CLR high
Rev.2.00 Jul. 20, 2004 page 6 of 10

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]