5962-8688001QA(1999) 查看數據表（PDF） - Intersil
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5962-8688001QA Datasheet PDF : 15 Pages
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HS-3282
AC Electrical Performance Specifications VDD = 5V ±5%, TA = 0oC to +70oC (HS-3282-5),
TA = -55oC to +125oC (HS-3282-8) (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
Data Word Gap Time 1/
Data Word Gap Time 2/
Data Transmission Word to TX/R Set Time
Enable Transmit Turnoff Time
REPEATER OPERATION TIMING
TGAP
TGAP
TDTX/R
TENTX/R
VDD = 4.75V, 5.25V
VDD = 4.75V, 5.25V
VDD = 4.75V, 5.25V
VDD = 4.75V, 5.25V
39.6
316.8
-
0
40.4
323.2
400
-
Data Enable to Parallel Load Delay Time
Data Enable Hold for Parallel Load Time
Enable Transmit Delay Time
NOTES:
1. 100kHz Data Rate.
2. 12.5kHz Data Rate.
TENPL
TPLEN
TTX/REN
VDD = 4.75V, 5.25V
VDD = 4.75V, 5.25V
VDD = 4.75V, 5.25V
0
-
0
-
0
-
UNITS
µs
µs
ns
ns
ns
ns
ns
Electrical Performance Specifications VDD = 5V ±5%, TA = 0oC to +70oC (HS-3282-5),
TA = -55oC to +125oC (HS-3282-8)
PARAMETER
SYMBOL
(NOTE 1)
CONDITIONS
LIMITS
MIN
MAX
UNITS
Differential Input Capacitance
Input Capacitance to VDD
lnput Capacitance to GND
Input Capacitance
Output Capacitance
Clock Rise Time
CD
CH
CG
Cl
CO
TLHC
VDD = Open, f = 1MHz, Note 2, 3
VDD = GND, f = 1MHz, Note 2, 3
VDD = Open, f = 1MHz, Note 2, 3
VDD = Open, f = 1MHz, Note 2, 4
VDD = Open, f = 1MHz, Note 2, 5
CLK = 1MHz, From 0.7V to 3.5V
-
20
pF
-
20
pF
-
20
pF
-
15
pF
-
15
pF
-
10
ns
Clock Fall Time
THLC
CLK = 1MHz, From 3.5V to 0.7V
-
10
ns
Input Rise Time
TLHI
From 0.7V to 3.5V, Note 6
-
15
ns
Input Fall Time
THLI
From 3.5V to 0.7V, Note 6
-
15
ns
NOTES:
1. The parameters listed in this table are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design and after major process and/or design changes affecting these parameters.
2. All measurements are referenced to device GND.
3. Pins 2-3, 4-5.
4. Pins 8-10, 28, 29, 33, 34, 37, 39.
5. Pins 6, 7, 11-20, 22-27, 30-32, 38.
6. Pins 8-20, 22-29, 33, 34.
5-193
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