HSDL-7000 查看數據表（PDF） - Avago Technologies
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HSDL-7000 Datasheet PDF : 6 Pages
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Recommended Operating Conditions
(TA= -40 to +85°C)
Parameter
Symbol
Supply Voltage
Input Voltage
Ambient Temperature
High Level Input Voltage
Low Level Input Voltage
Positive Trigger Voltage
Negative Trigger Voltage
Hysteresis Voltage
Power Dissipation
Input Rise Time
Input Fall Time
Max Clk Frequency (16XCLK)
Minimum Pulse Width (IR_TXD)*
VCC
VI
TA
VIH
VIL
VP
VN
VH
PDISS
tri
tfa
f16XCLK
tmpx
Min.
2.7
0.0
-40
0.7 VCC
0.0
1.61
0.55
0.50
250
Typ.
5.0
4.9
Max.
5.5
VCC
+85
VCC
0.3 VCC
4.00
3.10
2.00
220
200
200
2
Units
V
V
°C
V
V
V
V
V
mW
ns
ns
MHz
ns
Conditions
CMOS level
CMOS level
CMOS level
CMOS level
CMOS level
CMOS level
CMOS level
CMOS level
f16XCLK = 2 MHz
f16XCLK = 2 MHz
f16XCLK = 2 MHz
f16XCLK = 2 MHz
*IrDA Parameters. The Max Clk Frequency represents the maximum clock frequency to drive the HSDL-7000’s internal state machine.
Under normal circumstances, this clock input should not exceed 16 * 115.2 Kbp/s or 1.8432 MHz. This product can operate at higher
clock rates, but the above is the recommended rate.
The Minimum Pulse Width represents the minimum pulse width of the encoded IR_TXD pulse (and the IR_RCV pulse). As per the IrDA
specifications, the minimum pulse width of the IR_TXD and IR_RCV pulses should be 3 * (1/1.8432 MHz) or 1.63 µs. The minimum
pulse width specified for the HSDL-7000 is 250 ns, which is within IrDA specification. Under normal circumstances, the pulse width
should not be less than 1.63 µs.
Application Circuits
HSDL-7000 Connection to UART
SIR Transceivers
HSDL-7000
TXD
RCV
IR_TXD
IR_RCV
TXD
RCV
16XCLK
UART 16550
SOUT
SIN
BAUDOUT
At the time of this publication, Light Emitting Diodes (LEDs) that are contained in this product are
regulated for eye safety in Europe by the Commission for European Electrotechnical Standardization
(CENELEC) EN60825-1. Please refer to Application Brief I-008 for more information.
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