HYM64V2005GU-50 查看數據表（PDF） - Siemens AG

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HYM64V2005GU-50

3.3V 2M × 64-Bit EDO-DRAM Module 3.3V 2M x 72-Bit EDO-DRAM Module

Siemens AG 

HYM 64(72)V2005GU-50/-60

2M x 64/72 DRAM Module

AC Characteristics 5)6)

TA = 0 to 70 °C,VCC = 3.3 V ± 0.3 V, tT = 2 ns

Parameter

Symbol

Limit Values

Unit

-50

-60

min. max. min. max.

common parameters

Random read or write cycle time

RAS precharge time

RAS pulse width

CAS pulse width

Row address setup time

Row address hold time

Column address setup time

Column address hold time

RAS to CAS delay time

RAS to column address delay

RAS hold time

CAS hold time

CAS to RAS precharge time

Transition time (rise and fall)

Refresh period

tRC

84

tRP

30

tRAS

50

tCAS

8

tASR

0

tRAH

8

tASC

0

tCAH

8

tRCD

12

tRAD

10

tRSH

13

tCSH

40

tCRP

5

tT

1

tREF

–

–

104 –

ns

–

40

–

ns

10k 60

10k ns

10k 10

10k ns

–

0

–

ns

–

10

–

ns

–

0

–

ns

–

10

–

ns

37

14

45

ns

25

12

30

ns

15

–

ns

50

–

ns

–

5

–

ns

50

1

50

ns

32

–

32

ms

16E

Note

7

Read Cycle

Access time from RAS

tRAC

–

50

–

60

ns

8, 9

Access time from CAS

tCAC

–

13

–

15

ns

8, 9

Access time from column address

tAA

–

25

–

30

ns

8,10

OE access time

tOEA

–

13

–

15

ns

Column address to RAS lead time

tRAL

25

–

30

–

ns

Read command setup time

tRCS

0

–

0

–

ns

Read command hold time

tRCH

0

–

0

–

ns

11

Read command hold time referenced to tRRH

0

–

0

–

ns

11

RAS

CAS to output in low-Z

Output buffer turn-off delay

Output turn-off delay from OE

tCLZ

0

tOFF

0

tOEZ

0

–

0

13

0

13

0

–

ns

8

15

ns

12

15

ns

12

Semiconductor Group

9

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