HYS64V2100GU-10 查看數據表（PDF） - Siemens AG

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HYS64V2100GU-10

3.3V 2M x 64-Bit SDRAM Module 3.3V 2M x 72-Bit SDRAM Module

Siemens AG 

HYS64(72)V2100G(C)U-10

2M x 64/72 SDRAM-Module

Parameter

Symbol

Limit Values

Bank to Bank Delay Time

tRRD

CAS to CAS delay time (same bank) tCCD

min

20

1

-10

max

–

–

Unit Note

ns

CLK

Refresh Cycle

Self Refresh Exit Time

Refresh Period (4096 cycles)

tSREX

tREF

2Clk

+tRC

–

–

ns 8

64 ms 7

Read Cycle

Data Out Hold Time

tOH

Data Out to Low Impedance Time

tLZ

Data Out to High Impedance Time

tHZ

CAS Latency = 3

CAS Latency = 2

CAS Latency = 1

3

–

ns

0

–

ns

9

–

6

ns

–

8

ns

–

25 ns

DQM Data Out Disable Latency

tDQZ

2

–

CLK

Write Cycle

Data In Setup Time

Data In Hold Time

Data input to Precharge

Data In to Active/refresh

DQM Write Mask Latency

tDS

3

tDH

1

tDPL

2

tDAL

5

tDQW

0

–

ns

–

ns

–

CLK

–

CLK 10

–

CLK

Semiconductor Group

8

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