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HYS72V8000GU 查看數據表(PDF) - Siemens AG

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HYS72V8000GU Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
3.3V 8M x 64-Bit SDRAM Module
3.3V 8M x 72-Bit SDRAM Module
168 pin unbuffered DIMM Modules
HYS64V8000GU-10
HYS72V8000GU-10
168 Pin JEDEC Standard, Unbuffered 8 Byte Dual-In-Line SDRAM Modules
for PC main memory applications
1 bank 8M x 64, 8M x 72 organisation
Optimized for byte-write non-parity or ECC applications
Fully PC66 layout compatible
JEDEC standard Synchronous DRAMs (SDRAM)
Performance:
fCK
Max. Clock frequency
tAC
Max. access time from clock
-10
66 MHz @ CL=2
100 MHz @ CL=3
8 ns @ CL=2
7 ns @ CL=3
Single +3.3V(± 0.3V ) power supply
Programmable CAS Latency, Burst Length and Wrap Sequence
(Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
Decoupling capacitors mounted on substrate
All inputs, outputs are LVTTL compatible
Serial Presence Detect with E2PROM
Utilizes eight / nine 8M x 8 SDRAMs in TSOPII-54 packages
4096 refresh cycles every 64 ms
Gold contact pad
Card Size: 133,35mm x 25,40mm x 4,00 mm
Semiconductor Group
1
2.98

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