HYS72V8000GU 查看數據表（PDF） - Siemens AG

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HYS72V8000GU

3.3V 8M x 64-Bit SDRAM Module 3.3V 8M x 72-Bit SDRAM Module

Siemens AG 

HYS64(72)V8000GU-10

8M x 64/72 SDRAM-Module

Parameter

Symbol Limit Values Unit

Activate(a) to Activate(b) Command tRRD

period

CAS(a) to CAS(b) Command period tCCD

Mode Register Set-up time

tRSC

Power Down Mode Entry Time

tSB

-10

min

max

20

–

1

–

20

–

0

10

ns 6

CLK

ns

ns

Refresh Cycle

Refresh Period

(4096 cycles)

Self Refresh Exit Time

tREF

tSREX

–

64

ms

10

Read Cycle

Data Out Hold Time

Data Out to Low Impedance Time

Data Out to High Impedance Time

DQM Data Out Disable Latency

tOH

3

–

ns

tLZ

0

–

ns

tHZ

3

10

ns 8

tDQZ

2

–

CLK

Write Cycle

Write Recovery Time

CAS Latency = 3 tWR

CAS Latency = 2

DQM Write Mask Latency

tDQW

10

–

ns

15

–

ns

0

–

CLK

Semiconductor Group

8

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