LH77790B 查看數據表（PDF） - Sharp Electronics
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LH77790B Datasheet PDF : 32 Pages
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LH77790B
PINS
91
92
93
94
95
84 - 77
139 - 135, 128 - 126
149 - 145, 142 - 140
159 - 155, 152 - 150
98 - 96
114, 112, 108
115, 113, 111
150, 151
145, 146
142, 147
152
149
148
101
119
3
162
116
125
NAME
CP2
CP1
MCLK
S
LCDCNTL
VD[7:0]
PA[7:0]
PB[7:0]
PC[7:0]
PWM[2:0]
RxD[2:0]
TxD[2:0]
RTS[1:0]
CTS[1:0]
RI[1:0]
DTR0
DSR0
DCD0
RESETI**
RESETO
XCLK
XCLKDIS
UCLK
CTCLK
Table 1. Pin Descriptions
DIRECTION
DESCRIPTION
LCD CONTROLLER INTERFACE
O
Shift/Pixel Clock.
O
Line Pulse/HSYNC.
O
AC Modulation Signal.
O
Frame Pulse/VSYNC.
O
LCD Control Signal.
O
Video Data.
PROGRAMMABLE PERIPHERAL INTERFACE
Parallel ports A, B, and C signals. Signals have programmable access
I/O
and can function as Input, Output or Controls (port C only). PB[7:2] and
PC[2:0] are multiplexed with UARTs
modem signals.
PWM INTERFACE
O
Pulse Width Modulator output signals.
UARTs INTERFACE
I
UART serial data input signals. RxD2 also doubles as the digital input
for the IR interface.
O
UART serial data output signals. TxD2 also doubles as the digital output
for the IR interface.
O
Request To Send for UART0 and UART1. Multiplexed with PC0 and
PC1 respectively.
I
Clear To Send for UART0 and UART1. Multiplexed with PB3 and PB4
respectively.
I
Ring Indicator for UART0 and UART1. Multiplexed with PB2 and PB5
respectively.
O
Data Terminal Ready for UART0 only. Multiplexed with PC2.
I
Data Set Ready for UART0 only. Multiplexed with PB7.
I
Data Carrier Detect for UART0 only. Multiplexed with PB6.
RESET AND EXTERNAL CLOCKS
Chip and JTAG TAP Controller Reset Input. RESETI has a built-in glitch
I
detector. RESETO will be driven LOW after a valid reset is detected for
as long as RESETI is driven LOW. JTAG reset, TRST, is internally con-
nected to RESETI.
Chip Reset Output. It will be driven LOW during:
O
1. Chip Reset
2. WDT Timeout Reset
3. Software Controlled Reset
I
The 790B External Clock Input pin. Duty cycle is 50%.
XCLKDIS is an active HIGH output pin that can be used to disable ex-
ternal clock circuitry and will result in reducing current consumption to
O
micro-amperes. XCLKDIS is HIGH in Sleep and Stop modes. Connect-
ing this pin to the external clock circuitry, allows the 790B to go into Stop
mode by disabling the external clock.
I
UART/DASK Demodulator External clock input signal. Duty cycle is 50%.
I
Counter/Timer External clock input signal. Duty cycle is 50%.
6
Thermal & Electrical Specification
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