LH77790B
PINS
NAME
160
TCK
161
TMS
165
TDI
166
TDO
170
ADBE
167
TEST0
168
TEST1
171
TEST2
172
TEST3
9, 19, 29, 39, 53, 63,
75, 85, 99, 109, 129,
VCC
143, 153, 163, 173
4, 10, 20, 30, 40,
54, 64, 76, 86, 100,
110, 120, 130, 144,
VSS
154, 164, 174
1, 2, 43, 44, 45, 46,
87, 88, 89, 90, 131,
132, 133, 134,
NC
175, 176
Table 1. Pin Descriptions
DIRECTION
DESCRIPTION
JTAG INTERFACE*
JTAG Test/EmbeddedICE™ clock input signal. Must be pulled-up for
I
normal operation (56 kΩ is recommended for compatibility with ARM’s
EmbeddedICE)
JTAG Test/EmbeddedICE mode select input signal. Must be pulled-up
I
for normal operation (56 kΩ is recommended for compatibility with
ARM’s EmbeddedICE)
JTAG Test/EmbeddedICE data input signal. Must be pulled-up for
I
normal operation (56 kΩ is recommended for compatibility with ARM’s
EmbeddedICE)
O
JTAG Test/EmbeddedICE data output signal.
RESERVED INTERFACE
I
Reserved. Must be tied HIGH for normal operation.
I
Reserved. Must be tied LOW for normal operation.
O
Reserved. No Connect.
I
Reserved. Must be tied LOW for normal operation
O
Reserved. No Connect
POWER SIGNALS
I
Power. All LH77790B are 5 V/3.3 V.
I
Ground. All ground pins must be used.
NO CONNECT
—
No connection.
NOTE: *JTAG Reset, TRST, is internally connected to RESETI. IEEE 1149.1 – 1990 Standard requires JTAG Inputs to be pulled
up to a good logic level to achieve normal operations.
Thermal & Electrical Specification
7