LP62S4096EX-55LLI 查看數據表（PDF） - AMIC Technology

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LP62S4096EX-55LLI

512K X 8 BIT LOW VOLTAGE CMOS SRAM

AMIC Technology 

LP62S4096E-I Series

Truth Table

Mode

CE1

CE2

OE

WE

I/O Operation

Standby

H

X

X

X

High Z

Standby

X

L

X

X

High Z

Output Disable

L

H

H

H

High Z

Read

Write

L

H

L

H

L

H

X

L

DOUT

DIN

Note: X = H or L

Capacitance (TA = 25°C, f = 1.0MHz)

Symbol

Parameter

Min.

Max.

Unit

CIN*

CI/O*

Input Capacitance

Input/Output Capacitance

6

pF

8

pF

* These parameters are sampled and not 100% tested.

Supply Current

ISB, ISB1

ISB, ISB1

ICC, ICC1, ICC2

ICC, ICC1, ICC2

ICC, ICC1, ICC2

Conditions

VIN = 0V

VI/O = 0V

AC Characteristics (TA = -40°C to + 85°C, VCC = 2.7V to 3.6V)

Symbol

Parameter

LP62S4096E-55LLI LP62S4096E-70LLI Unit

Read Cycle

tRC

Read Cycle Time

tAA

Address Access Time

tACE1, tACE2 Chip Enable Access Time

tOE

Output Enable to Output Valid

tCLZ1, tCLZ2 Chip Enable to Output in Low Z

tOLZ

Output Enable to Output in Low Z

tCHZ1, tCHZ2 Chip Disable to Output in High Z

tOHZ

Output Disable to Output in High Z

tOH

Output Hold from Address Change

Min.

Max.

Min.

Max.

55

-

70

-

ns

-

55

-

70

ns

-

55

-

70

ns

-

30

-

35

ns

10

-

10

-

ns

5

-

5

-

ns

0

20

0

25

ns

0

20

0

25

ns

5

-

5

-

ns

(January, 2002, Version 2.0)

5

AMIC Technology, Inc.

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