LP62S4096EX-55LLI 查看數據表（PDF） - AMIC Technology

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LP62S4096EX-55LLI

512K X 8 BIT LOW VOLTAGE CMOS SRAM

AMIC Technology 

Write Cycle 2(6)

(Chip Enable Controlled)

Address

CE1

tWC

tAS1

(4)

tAW

tCW1 , tCW2

CE2

WE

DIN

DOUT

tWP2

tDW

tWHZ7

LP62S4096E-I Series

tWR3

tDH

Notes: 1. tAS is measured from the address valid to the beginning of Write.

2. A Write occurs during the overlap (tWP) of a low CE1 or high CE2 , and a low WE .

3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low WE going high to the end of the

Write cycle.

4. If the CE1 low or CE2 high transition occurs simultaneously with the WE low transition or after the WE transition

, outputs remain in a high impedance state.

5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.

6. OE level is high or low.

7. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.

(January, 2002, Version 2.0)

9

AMIC Technology, Inc.

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